LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 183

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 107. Pin description
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
<Document ID>
User manual
Symbol
VDDIO
VSS
VSSIO
VSSA
Not connected
-
x = available; - = not pinned out.
I = input, O = output, IA = inactive; PU = pull-up enabled (weak pull-up resistor pulls up pin to V
5 V tolerant pad with 15 ns glitch filter; provides digital I/O functions with TTL levels and hysteresis; normal drive strength.
5 V tolerant pad with 15 ns glitch filter providing digital I/O functions with TTL levels, and hysteresis; high drive strength.
5 V tolerant pad with 15 ns glitch filter providing high-speed digital I/O functions with TTL levels and hysteresis.
5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output. When configured as a ADC
input or DAC output, the pin is not 5 V tolerant and the digital section of the pad must be disabled by setting the pin to an input function
and disabling the pull-up resistor through the pin’s SFSP register.
5 V tolerant transparent analog pad.
Transparent analog pad. Not 5 V tolerant.
Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode
only). This pad is not 5 V tolerant.
D7,
E12,
F7,
F8,
G10,
H10,
J6,
J7,
K7,
L9,
L10,
N7,
N13
G9,
H7,
J10,
J11,
K8
C4,
D13,
G6,
G7,
G8,
H8,
H9,
J8,
J9,
K9,
K10,
M13,
P7,
P13
B2
B9
x
x
x
x
…continued
x
x
x
x
x
x
x
x
5,
36,
41,
71,
77,
107,
111,
141
-
4,
40,
76,
109
135
All information provided in this document is subject to legal disclaimers.
[12]
[12]
Rev. 00.13 — 20 July 2011
Reset
state
[2]
-
-
-
-
-
Type Description
-
-
-
-
-
I/O power supply.
Ground.
Ground.
Analog ground.
n.c.
Chapter 12: LPC18xx Pin configuration
DD(IO)
); F = floating
UM10430
© NXP B.V. 2011. All rights reserved.
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