LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 387

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 329. OTG Status and Control register (OTGSC - address 0x4000 61A4) bit description
<Document ID>
User manual
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Symbol Value
VD
VC
HAAR
OT
DP
IDPU
HADP
HABA
ID
AVV
ASV
BSV
BSE
MS1T
DPS
-
0
1
0
1
0
1
0
1
-
The status inputs are debounced using a 1 msec time constant. Values on the status
inputs that do not persist for more than 1 msec will not cause an update of the status input
register or cause an OTG interrupt.
Description
VBUS_Discharge
Setting this bit to 1 causes VBUS to discharge through a resistor.
VBUS_Charge
Setting this bit to 1 causes the VBUS line to be charged. This is used for
VBUS pulsing during SRP.
Hardware assist auto_reset
Disabled
Enable automatic reset after connect on host port.
OTG termination
This bit must be set to 1 when the OTG controller is in device mode. This
controls the pull-down on USB_DM.
Data pulsing
Setting this bit to 1 causes the pull-up on USB_DP to be asserted for data
pulsing during SRP.
ID pull-up.
This bit provides control over the pull-up resistor.
Pull-up off. The ID bit will not be sampled.
Pull-up on.
Hardware assist data pulse
Write a 1 to start data pulse sequence.
Hardware assist B-disconnect to A-connect
Disabled.
Enable automatic B-disconnect to A-connect sequence.
USB ID
A-device
B-device
A-VBUS valid
Reading 1 indicates that VBUS is above the A-VBUS valid threshold.
A-session valid
Reading 1 indicates that VBUS is above the A-session valid threshold.
B-session valid
Reading 1 indicates that VBUS is above the B-session valid threshold.
B-session end
Reading 1 indicates that VBUS is below the B-session end threshold.
1 millisecond timer toggle
This bit toggles once per millisecond.
Data bus pulsing status
Reading a 1 indicates that data bus pulsing is detected on the port.
reserved
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
UM10430
Reset
value
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
© NXP B.V. 2011. All rights reserved.
387 of 1164
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO