LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 627

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
25.7.7 Timer match registers (MR0 - MR3)
Table 539. Timer match control registers MCR (MCR - addresses 0x4008 4014 (TIMER0),
The Match register values are continuously compared to the Timer Counter value. When
the two values are equal, actions can be triggered automatically. The action possibilities
are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are
controlled by the settings in the MCR register.
Table 540. Timer match registers MR0 to 3 (MR, addresses 0x4008 4018 (MR0) to 0x4008
Bit
6
7
8
9
10
11
31:12 -
Bit
31:0
Symbol Value Description
MR2I
MR2R
MR2S
MR3I
MR3R
MR3S
Symbol
MATCH
0x4008 5014 (TIMER1), 0x400C 3014 (TIMER2), 0x400C 4014 (TIMER3)) bit
description
4024 (M3) (TIMER0), 0x4008 5018 (MR0) to 0x4008 5024 (MR3)(TIMER1),
0x400C 3018 (MR0) to 0x400C 8024 (MR3) (TIMER2), 0x400C 4018 (MR0) to 0x400C
4024 (MR3)(TIMER3)) bit description
All information provided in this document is subject to legal disclaimers.
1
0
1
0
1
0
1
0
1
0
1
0
Rev. 00.13 — 20 July 2011
…continued
Interrupt on MR2
Interrupt is generated when MR2 matches the value in the TC.
Interrupt is disabled
Reset on MR2
TC will be reset if MR2 matches it.
Feature disabled.
Stop on MR2.
TC and PC will be stopped and TCR[0] will be set to 0 if MR2
matches the TC
Feature disabled.
Interrupt on MR3
Interrupt is generated when MR3 matches the value in the TC.
This interrupt is disabled
Reset on MR3
TC will be reset if MR3 matches it.
Feature disabled.
Stop on MR3
TC and PC will be stopped and TCR[0] will be set to 0 if MR3
matches the TC.
Feature disabled.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Description
Timer counter match value.
Chapter 25: LPC18xx Timer0/1/2/3
UM10430
© NXP B.V. 2011. All rights reserved.
627 of 1164
Reset
value
0
Reset
value
0
0
0
0
0
0
NA