LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1074

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 1008.I2S transmit modes
<Document ID>
User manual
DAO bit
5
0
0
0
0
1
1
1
TXMODE
bits [3:0]
0 0 0 0
0 0 1 0
0 1 0 0
1 0 0 0
0 0 0 0
0 0 1 0
0 1 0 0
42.9.7.2 I
The clocking and WS usage of the I2S interface is configurable. In addition to master and
slave modes, which are independently configurable for the transmitter and the receiver,
several different clock sources are possible, including variations that share the clock
and/or WS between the transmitter and receiver. This last option allows using I2S with
fewer pins, typically four.
Many configurations are possible that are not considered useful, the following tables and
figures give details of the configurations that are most likely to be useful.
Description
Typical transmitter master mode. See
The I2S transmit function operates as a master.
The transmit clock source is the fractional rate divider.
The WS used is the internally generated TX_WS.
The TX_MCLK pin is not enabled for output.
Transmitter master mode sharing the receiver reference clock. See
The I2S transmit function operates as a master.
The transmit clock source is RX_REF.
The WS used is the internally generated TX_WS.
The TX_MCLK pin is not enabled for output.
4-wire transmitter master mode sharing the receiver bit clock and WS. See
The I2S transmit function operates as a master.
The transmit clock source is the RX bit clock.
The WS used is the internally generated RX_WS.
The TX_MCLK pin is not enabled for output.
Transmitter master mode with TX_MCLK output. See
The I2S transmit function operates as a master.
The transmit clock source is the fractional rate divider.
The WS used is the internally generated TX_WS.
The TX_MCLK pin is enabled for output.
Typical transmitter slave mode. See
The I2S transmit function operates as a slave.
The transmit clock source is the TX_SCK pin.
The WS used is the TX_WS pin.
Transmitter slave mode sharing the receiver reference clock. See
The I2S transmit function operates as a slave.
The transmit clock source is RX_REF.
The WS used is the TX_WS pin.
4-wire transmitter slave mode sharing the receiver bit clock and WS. See
The I2S transmit function operates as a slave.
The transmit clock source is the RX bit clock.
The WS used is RX_WS ref.
2
S operating modes
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Figure
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Figure
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Figure
Chapter 42: Appendix
161.
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Figure
UM10430
© NXP B.V. 2011. All rights reserved.
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