LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 499

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
22.6.19 DMA Receive poll demand register
22.6.20 DMA Receive descriptor list address register
22.6.21 DMA Transmit descriptor list address register
The Receive Poll Demand register enables the receive DMA to check for new descriptors.
This command is given to wake up the RxDMA from SUSPEND state. The RxDMA can go
into SUSPEND state only due to the unavailability of descriptors owned by it.
Table 424. DMA Receive poll demand register (DMA_REC_POLL_DEMAND, address 0x4001
The Receive Descriptor List Address register points to the start of the Receive Descriptor
List. The descriptor lists reside in the host’s physical memory space and must be
Word/Dword/Lword-aligned (for 32/64/128- bit data bus). The DMA internally converts it to
bus width aligned address by making the corresponding LS bits low. Writing to this
register is permitted only when reception is stopped. When stopped, this register must be
written to before the receive Start command is given.
Table 425. DMA Receive descriptor list address register (DMA_REC_DES_ADDR, address
The Transmit Descriptor List Address register points to the start of the Transmit Descriptor
List. The descriptor lists reside in the host’s physical memory space and must be
Word/DWORD/LWORD-aligned (for 32/64/128-bit data bus). The DMA internally converts
it to bus width aligned address by making the corresponding LSB to low. Writing to this
register is permitted only when transmission has stopped. When stopped, this register can
be written before the transmission Start command is given.
Bit
31:0
Bit
31:0
Symbol
RPD
Symbol
SRL
1008) bit description
0x4001 100C) bit description
All information provided in this document is subject to legal disclaimers.
Description
Receive poll demand
When these bits are written with any value, the DMA reads
the current descriptor pointed to by the Current Host
Receive Descriptor register
descriptor is not available (owned by Host), reception
returns to the Suspended state and bit 7 in the DMA_STAT
Register is not asserted. If the descriptor is available, the
Receive DMA returns to active state.
Description
Start of receive list
This field contains the base address of the First Descriptor
in the Receive Descriptor list. The LSB bits [1/2/3:0] for
32/64/128-bit bus width) will be ignored and taken as
all-zero by the DMA internally. Hence these LSB bits are
Read Only.
Rev. 00.13 — 20 July 2011
(Section
22.6.28). If that
Chapter 22: LPC18xx Ethernet
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
Reset
value
0
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Access
RO/WT
Access
R/W