LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 426

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.10.10 Managing queue heads
20.10.9.2 Isochronous endpoint bus response matrix
Remark: Priming an endpoint towards the end of (micro) frame N-1 will not guarantee
delivery in (micro) frame N. The delivery may actually occur in (micro) frame N+1 if device
controller does not have enough time to complete the prime before the SOF for packet N
is received.
Table 353. Isochronous endpoint bus response matrix
[1]
[2]
The device queue head (dQH) points to the linked list of transfer tasks, each depicted by
the device Transfer Descriptor (dTD). An area of memory pointed to by
ENDPOINTLISTADDR contains a group of all dQH’s in a sequential list as shown
Figure
(OUT/SETUP) and the odd elements are used for transmit endpoints (IN/INTERRUPT).
Device transfer descriptors are linked head to tail starting at the queue head and ending at
a terminate bit. Once the dTD has been retired, it will no longer be part of the linked list
Token
type
Setup
In
Out
Ping
Invalid
Fig 40. Endpoint queue head diagram
BS error = Force Bit Stuff Error
NULL packet = Zero length packet.
ENDPOINTLISTADDR
40. The even elements in the list of dQH’s are used for receive endpoints
STALL
STALL
NULL
packet
Ignore
Ignore
Ignore
All information provided in this document is subject to legal disclaimers.
Not primed
STALL
NULL packet
Ignore
Ignore
Ignore
Endpoint Queue Heads
Endpoint dQH0 - Out
Endpoint dQH1 - Out
Endpoint dQH0 - In
Rev. 00.13 — 20 July 2011
dQH
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
Primed
STALL
Transmit
Receive
Ignore
Ignore
Endpoint Transfer
Descriptors dTD
dTD
dTD
dTD
transfer buffer
transfer buffer
pointer
Underflow
n/a
BS error
n/a
Ignore
Ignore
pointer
transfer buffer
pointer
dTD
TRANSFER
BUFFER
TRANSFER
BUFFER
UM10430
TRANSFER
© NXP B.V. 2011. All rights reserved.
BUFFER
transfer buffer
pointer
Overflow
n/a
n/a
Drop packet
Ignore
Ignore
TRANSFER
BUFFER
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