LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 686

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
28.6 RI timer operation
<Document ID>
User manual
28.5.4 RI Counter register
Table 609. RI Control register (CTRL - address 0x400C 0008) bit description
Table 610. RI Counter register (COUNTER - address 0x400C 000C) bit description
Following reset, the counter begins counting up from 0x00000000. Whenever the counter
value equals the value programmed into the RICOMPVAL register the interrupt flag will be
set. Any bit or combination of bits can be removed from this comparison (i.e. forced to
compare) by writing a ‘1’ to the corresponding bit(s) in the RIMASK register. If the
enable_clr bit is low (default state), a valid comparison ONLY causes the interrupt flag to
be set. It has no effect on the count sequence. Counting continues as usual. When the
counter reaches 0xFFFFFFFF it rolls-over to 0x00000000 on the next clock and continues
counting. If the enable_clr bit is set to ‘1’ a valid comparison will also cause the counter to
be reset to zero. Counting will resume from there on the next clock edge.
Counting can be halted in software by writing a ‘0’ to the Enable_Timer bit - RICTRL(2).
Counting will also be halted when the processor is halted for debugging provided the
Enable_Break bit – RICTRL(1) is set. Both the Enable_Timer and Enable_Break bits are
set on reset.
The interrupt flag can be cleared in software by writing a ‘1’ to the Interrupt bit –
RICTRL(0).
Software can load the counter to any value at any time by writing to RICOUNTER.
The counter (RICOUNTER), RICOMPVAL register, RIMASK register and RICTRL register
can all be read by software at any time.
Bit
2
3
31:4
Bit
31:0
Symbol
RITENBR
RITEN
-
Symbol
RICOUNTER
All information provided in this document is subject to legal disclaimers.
Value
1
0
1
0
-
Description
32-bit up counter. Counts continuously unless RITEN bit in
RICTRL register is cleared or debug mode is entered (if enabled
by the RITNEBR bit in RICTRL). Can be loaded to any value in
software.
Rev. 00.13 — 20 July 2011
Description
Timer enable for debug
The timer is halted when the processor is halted for
debugging.
Debug has no effect on the timer operation.
Timer enable.
Timer enabled.
Remark: This can be overruled by a debug halt if enabled in
bit 2.
Timer disabled.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Chapter 28: LPC18xx Repetitive Interrupt Timer (RIT)
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
1
1
NA
Reset
value
0