LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 255

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
15.5.1.8 Pin interrupt rising edge register
15.5.1.9 Pin interrupt falling edge register
Table 177. Pin interrupt active level (falling edge interrupt) clear register (CIENF, address
This register contains ones for pin interrupts selected in the PINTSEL registers (see
Table 130
register clears rising edge detection. Ones in this register assert an interrupt request for
pins that are enabled for rising-edge interrupts. All edges are detected for all pins selected
by the PINTSEL registers, regardless of whether they are interrupt-enabled.
Table 178. Pin interrupt rising edge register (RISE, address 0x4008 701C) bit description
This register contains ones for pin interrupts selected in the PINTSEL registers (see
Table 130
register clears falling edge detection. Ones in this register assert an interrupt request for
pins that are enabled for falling-edge interrupts. All edges are detected for all pins
selected by the PINTSEL registers, regardless of whether they are interrupt-enabled.
Table 179. Pin interrupt falling edge register (FALL, address 0x4008 7020) bit description
Bit
7:0
31:8
Bit
7:0
31:8 -
Bit
7:0
31:8
Symbol
RDET
Symbol Description
CENAF
-
Symbol Description
FDET
-
and
and
0x4008 7018) bit description
Table
Table
All information provided in this document is subject to legal disclaimers.
Ones written to this address clears bits in the IENF, thus
disabling interrupts. Bit n clears bit n in the IENF register.
0 = No operation.
1 = LOW-active interrupt selected or falling edge interrupt
disabled.
Reserved.
Description
Rising edge detect. Bit n detects the rising edge of the pin
selected in PINTSELn.
Read 0: No rising edge has been detected on this pin since
Reset or the last time a one was written to this bit.
Write 0: no operation.
Read 1: a rising edge has been detected since Reset or the
last time a one was written to this bit.
Write 1: clear rising edge detection for this pin.
Reserved.
Falling edge detect. Bit n detects the falling edge of the pin
selected in PINTSELn.
Read 0: No falling edge has been detected on this pin since
Reset or the last time a one was written to this bit.
Write 0: no operation.
Read 1: a falling edge has been detected since Reset or the
last time a one was written to this bit.
Write 1: clear falling edge detection for this pin.
Reserved.
131) on which a rising edge has been detected. Writing ones to this
131) on which a falling edge has been detected. Writing ones to this
Rev. 00.13 — 20 July 2011
Chapter 15: LPC18xx GPIO
UM10430
© NXP B.V. 2011. All rights reserved.
-
Reset
value
0
-
Reset
value
0
Reset
value
NA
-
255 of 1164
Access
R/W
-
Access
R/W
-
Access
WO
-