LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 380

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 326. Port Status and Control register in device mode (PORTSC1_D - address 0x4000 6184) bit description
<Document ID>
User manual
Bit
5:4
6
7
8
9
11:10 -
12
13
15:14 PIC1_0
Symbol
-
FPR
SUSP
PR
HSP
-
-
Value Description
-
0
1
0
1
0
1
0
1
-
-
-
0x0
0x1
0x2
0x3
Force port resume
Suspend
High-speed status
Reserved
Port indicator control
Port indicators are off.
undefined
Reserved
After the device has been in Suspend State for 5 ms or more, software
must set this bit to one to drive resume signaling before clearing. The
Device Controller will set this bit to one if a J-to-K transition is detected
while the port is in the Suspend state. The bit will be cleared when the
device returns to normal operation. When this bit transitions to a one
because a J-to-K transition detected, the Port Change Detect bit in the
USBSTS register is set to one as well.
No resume (K-state) detected/driven on port.
Resume detected/driven on port.
In device mode, this is a read-only status bit .
Port not in suspend state
Port in suspend state
Port reset
In device mode, this is a read-only status bit. A device reset from the USB
bus is also indicated in the USBSTS register.
Port is not in the reset state.
Port is in the reset state.
Remark: This bit is redundant with bits 27:26 (PSPD) in this register. It is
implemented for compatibility reasons.
Host/device connected to the port is not in High-speed mode.
Host/device connected to the port is in High-speed mode.
Not used in device mode.
Not used in device mode.
Writing to this field effects the value of the USB0_IND[1:0] pins.
amber
green
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
UM10430
Reset
value
0
0
0
0
0
-
00
© NXP B.V. 2011. All rights reserved.
380 of 1164
RO
Access
R/W
RO
RO
RO
-
R/W