NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 105

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.3.4
5.3.4.1
Table 38.
Table 39.
5.3.5
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Summary of DMA Transfer Sizes
Table 39
Word Count Register” indicates that the register contents represents either the number
of bytes to transfer or the number of 16-bit words to transfer. The column labeled
“Current Address Increment/Decrement” indicates the number added to or taken from
the Current Address register after each DMA transfer cycle. The DMA Channel Mode
Register determines when the Current Address Register will be incremented or
decremented.
Address Shifting When Programmed for 16-Bit I/O Count
by Words
DMA Transfer Size
The Intel
the PC-AT which used the 8237. The DMA shifts the addresses for transfers to/from a
16-bit device count-by-words. Note that the least significant bit of the Low Page
Register is dropped in 16-bit shifted mode. When programming the Current Address
Register (when the DMA channel is in this mode), the Current Address must be
programmed to an even address with the address value shifted right by one bit. The
address shifting is described in
Address Shifting in 16-bit I/O DMA Transfers
Autoinitialize
By programming a bit in the DMA Channel Mode Register, a channel may be set up as
an autoinitialize channel. When a channel undergoes autoinitialization, the original
values of the Current Page, Current Address and Current Byte/Word Count Registers
are automatically restored from the Base Page, Address, and Byte/Word Count
Registers of that channel following TC. The Base Registers are loaded simultaneously
with the Current Registers by the microprocessor when the DMA channel is
programmed and remain unchanged throughout the DMA service. The mask bit is not
set when the channel is in autoinitialize. Following autoinitialize, the channel is ready to
perform another DMA service, without processor intervention, as soon as a valid DREQ
is detected.
8-Bit I/O, Count By Bytes
16-Bit I/O, Count By Words (Address
Shifted)
NOTE: The least significant bit of the Page Register is dropped in 16-bit shifted mode.
DMA Device Date Size And Word Count
®
lists each of the DMA device transfer sizes. The column labeled “Current Byte/
A[23:17]
Address
6300ESB ICH maintains compatibility with the implementation of the DMA in
Output
A[16:1]
A0
Table
8-Bit I/O Programmed
Address (Ch 0–3)
39.
A[23:17]
A[16:1]
A0
Current Byte/Word
Count Register
Words
Bytes
Intel
16-Bit I/O Programmed
®
Address (Ch 5–7)
6300ESB I/O Controller Hub
Current Address
(Shifted)
A[23:17]
A[15:0]
Increment/
Decrement
0
1
1
105
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