NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 130

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 52.
Intel
DS
130
®
6300ESB I/O Controller Hub
Lowest Priority Message (Without Focus Processor)
NOTES:
Cycle
1. Cycle 21 through 28 are used to arbitrate for the lowest priority processor. The processor that
2. Cycles 29 through 32 are used to break tie in case two more processors have lowest priority.
2 - 5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
1
6
7
8
9
takes part in the arbitration drives the processor priority on the bus. Only the local APICs that
have “free interrupt slots” will participate in the lowest priority arbitration.
The bus arbitration ID's are used to break the tie.
NOT(DM)
NOT(M1)
NOT(D7)
NOT(D5)
NOT(D3)
NOT(D1)
NOT(V7)
NOT(V5)
NOT(V3)
NOT(V1)
NOT(C1)
NOT(A1)
NOT(A)
NOT(L)
ArbID3
ArbID2
ArbID1
ArbID0
ARBID
Bit 1
P7
P6
P5
P4
P3
P2
P1
P0
1
1
S
1
NOT(M2)
NOT(M0)
NOT(TM)
NOT(D6)
NOT(D4)
NOT(D2)
NOT(D0)
NOT(V6)
NOT(V4)
NOT(V2)
NOT(V0)
NOT(C0)
NOT(A1)
NOT(A)
Bit 0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
S
1
Normal Arbitration
Arbitration ID
DM = Destination Mode from bit 11 of the redirection
table register.
M2-M0 = Delivery Mode from bits 10:8 of the redirection
table register.
L = Level, TM = Trigger Mode
Interrupt vector bits V7 - V0 from redirection table
register.
Destination field from bits 63:56 of redirection table
register.
Checksum for Cycles 6 - 16
Postamble
Status Cycle 0.
Status Cycle 1.
Inverted Processor Priority P7 - P0
Status
Idle
Comments
Order Number: 300641-004US
Intel
®
6300ESB ICH—5
November 2007