NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 707

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

19—Intel
19.4.2
19.4.3
19.4.3.1 I/O Transfers
Table 633. I/O Sync Bits Description
19.5
19.5.1
November 2007
Order Number: 300641-004US
Note: LPC bus signals from SIU are tied to primary LPC interface external to the Intel
®
6300ESB ICH
Reset Policy
The following rules govern the reset policy:
6300ESB ICH device. Host LPC and SIU LPC names are used interchangeably
throughout.
LPC Transfers
These will generally be used for register or FIFO accesses, and will generally have
minimal Sync times. The minimum number of wait-states between bytes is 1. Data
transfers are assumed to be exactly 1 byte. The host is responsible for breaking up
larger data transfers into 8 bit cycles.
Logical Device 4 and 5: Serial Ports (UARTs)
This section describes the Universal Asynchronous Receiver/Transmitter (UART) serial
port used for the two UARTs integrated into the SIU. The UART may be controlled
through programmed I/O. The basic programming model is the same for both UARTs
with the only difference being the Logical Device Number assigned to each.
Overview
The serial port consists of a UART which supports all the functions of a standard 16550
UART including hardware flow control interface.
The UART performs serial-to-parallel conversion on data characters received from a
peripheral device or a modem and parallel-to-serial conversion on data characters
received from the processor. The processor may read the complete status of the UART
at any time during the functional operation. Available status information includes the
type and condition of the transfer operations being performed by the UART and any
error conditions (parity, overrun, framing, or break interrupt).
•
•
The SIU reset (active low) is internally tied to the PCI bus reset.
When the SIU reset goes active (low):
0000
0101
0110
1010
Bits
— The host drives the LFRAME# signal high, tristates the LAD[3:0] signals, and ignores the
— The SIU ignores LFRAME#, tristates the LAD[3:0] pins and drives the SIU’s LDRQ# signal
LDRQ# signal.
inactive (high).
Sync Achieved with no error.
Indicates that Sync not Achieved yet, but the part is driving the bus.
Indicates that Sync not Achieved yet, but the part is driving the bus, and expect
long Sync.
Special Case: Peripheral indicating errors.
Indication
Intel
®
6300ESB I/O Controller Hub
®
707
DS