NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 686

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18.7.5.2 Non-Posted
18.7.5.3 Fast Back-to-Back
18.7.6
18.7.6.1 Prefetchable
18.7.6.2 Delayed
18.7.7
18.7.7.1 Normal Master Termination
18.7.7.2 Master Abort Termination
Intel
DS
686
®
6300ESB I/O Controller Hub
Note: Configuration cycles are not allowed to cross a bridge per the PCI bridge specification.
The Intel
Delayed write forwarding is not used. It is only for I/O write transactions. Since the
Intel
cycles all result in a master abort.
The Intel
Read Transactions
Any memory read multiple command on PCI that is decoded by the Intel
ICH is prefetched on the Hub Interface. Prefetching may be optionally disabled when bit
4 of the Intel
6300ESB ICH does not prefetch past a 4 Kbyte page boundary.
All memory read transactions are delayed read transactions. When the Intel
ICH accepts a delayed read request, it samples the address, command, and address
parity. This information is entered into the delayed transaction queue and all I/O
transactions then master abort.
Transaction Termination
As a PCI master, the Intel
returned by the target within five clock cycles of PXFRAME# assertion. It terminates a
transaction when the following conditions are met:
When an Intel
within five clocks of PXFRAME# assertion, the Intel
transaction with a master abort. The Intel
abort bit in the status register corresponding to the target bus.
•
•
•
•
•
The initiator terminates the transaction by de-asserting PXFRAME# and PXIRDY#.
A 4 Kbyte page boundary is reached.
The posted write data buffer fills up.
All write data for the transaction is transferred from the Intel
buffers to the target.
The master latency timer expires and the Intel
asserted.
®
6300ESB ICH does not support I/O write transactions across a bridge, these
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®
6300ESB ICH disconnects a write transaction when:
6300ESB ICH allows fast back-to-back write transactions on PCI.
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®
6300ESB ICH Configuration Register (offset 40-41h) is set. The Intel
6300ESB ICH initiated transaction is not responded to with DEVSEL#
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6300ESB ICH uses normal termination when DEVSEL# is
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6300ESB ICH sets the received master
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6300ESB ICH’s bus grant is de-
6300ESB ICH terminates the
Order Number: 300641-004US
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Intel
6300ESB ICH data
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6300ESB ICH—18
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November 2007
6300ESB
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6300ESB
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