NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 97

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.1.7
5.2
November 2007
Order Number: 300641-004US
®
6300ESB ICH
PCI Dual Address Cycle (DAC) Support
The Intel
main memory. This allows PCI masters to generate an address up to 44 bits. The size of
the actual supported memory space will be determined by the Memory Controller and
the processor.
The DAC mode is only supported for PCI adapters and USB EHCI, and is not supported
for any of the internal PCI masters (IDE, USB UHCI, AC’97, 8237 DMA, etc.).
When a PCI master wants to initiate a cycle with an address above 4G, it follows the
following behavioral rules (See PCI Local Bus Specification, Revision 2.2, section 3.9 for
more details):
LPC Bridge (with System and Management
Functions) (D31:F0)
The LPC Bridge function of the Intel
0. In addition to the LPC bridge function, D31:F0 contains other functional units
including DMA, Interrupt Controllers, Timers, Power Management, System
Management, GPIO, and RTC.
1. On the first clock of the cycle (when FRAME# is first active), the peripheral uses the
2. Also during the first clock, the peripheral drives the AD[31:0] signals with the low
3. On the second clock, the peripheral drives AD[31:0] with the high address. The
4. The rest of the cycle proceeds normally.
DAC encoding on the C/BE# signals. This unique encoding is: 1101.
address.
address is right justified: A[43:32] appear on AD[12:0]. The value of AD[31:13] is
expected to be 0, however the Intel
indicate the bus command type (Memory Read, Memory Write, etc.)
®
6300ESB ICH supports DAC format on PCI for cycles from PCI initiators to
®
6300ESB ICH resides in PCI Device 31:Function
®
6300ESB ICH will ignore these bits. C/BE#
Intel
®
6300ESB I/O Controller Hub
DS
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