NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 670

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Intel
DS
670
Bits
02
01
0
®
Table 604. Offset 3E: BCTRL—Bridge Control (Sheet 3 of 3)
6300ESB I/O Controller Hub
Enable (SE)
Parity Error
ISA Enable
Device
PXSERR#
Response
Offset
(PERE)
Name
Enable
(IE)
28
3E
Modifies the response by the bridge to ISA I/O addresses.
This only applies to I/O addresses that are enabled by the I/O
Base and I/O Limit registers and are in the first 64 Kbytes of
PCI-X I/O space. When this bit is set, the bridge blocks any
forwarding from primary to secondary of I/O transactions
addressing the last 768 bytes in each 1 Kbyte block (offsets
100h to 3FFh). This bit has no effect on transfers originating
on the secondary bus as the Intel
forward I/O transactions across the bridge.
When set, the bridge is enabled for SERR reporting.
Controls the Intel
data parity errors on the secondary interface. When the bit is
cleared, the bridge must ignore any parity errors that it
detects and continue normal operation. The Intel
ICH must generate parity even when parity error reporting is
disabled.
®
6300ESB ICH's response to address and
Description
®
6300ESB ICH does not
Attribute:
Function
Size:
®
0
Read/Write
16-bit
6300ESB
Order Number: 300641-004US
Reset
Value
Intel
0
0
0
®
6300ESB ICH—18
November 2007
Access
R/W
R/W
R/W