NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 752

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

20.1.23 Offset 4A - 4Bh: SDMA_TIM—Synchronous DMA
Intel
DS
752
15:1
13:1
11:1
Bits
Default Value:
9:8
7:6
4
2
0
®
Table 682. Offset 4A - 4Bh: SDMA_TIM—Synchronous DMA Timing Register
6300ESB I/O Controller Hub
Device:
Secondary Drive 1 Cycle
Secondary Drive 0 Cycle
Offset:
Time (SCT1)
Time (SCT0)
Timing Register (SATA–D31:F2)
(SATA–D31:F2) (Sheet 1 of 2)
Reserved
Reserved
Reserved
31
4A-4Bh
0000h
Name
Reserved.
For Ultra ATA mode. The setting of these bits determines the
minimum write strobe cycle time (CT). The DMARDY#-to-
STOP (RP) time is also determined by the setting of these
bits.
SCB1 = 0 (33MHz clk)
00 = CT 4 clocks, RP 6 clocks
01 = CT 3 clocks, RP 5 clocks
10 = CT 2 clocks, RP 4 clocks
11 = Reserved
SCB1 = ’1’ (66MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 8 clocks
10 = CT 2 clocks, RP 8 clocks
11 = Reserved
FAST_SCB1 = ’1’ (133MHz clk)
00 = Reserved
01 = CT 3 clks, RP 16 clks
10 = Reserved
11 = Reserved
Reserved.
For Ultra ATA mode. The setting of these bits determines the
minimum write strobe cycle time (CT). The DMARDY#-to-
STOP (RP) time is also determined by the setting of these
bits.
SCB1 = 0 (33MHz clk)
00 = CT 4 clocks, RP 6 clocks
01 = CT 3 clocks, RP 5 clocks
10 = CT 2 clocks, RP 4 clocks
11 = Reserved
SCB1 = ’1’ (66MHz clk)
00 = Reserved
01 = CT 3 clocks, RP 8 clocks
10 = CT 2 clocks, RP 8 clocks
11 = Reserved
FAST_SCB1 = ’1’ (133MHz clk)
00 = Reserved
01 = CT 3 clks, RP 16 clks
10 = Reserved
11 = Reserved
Reserved.
Description
Attribute:
Function:
Size:
2
Read/Write
16-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—20
November 2007
Access
R/W
R/W