NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 402

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 290. GPE0_STS—General Purpose Event 0 Status Register (Sheet 2 of 3)
Intel
DS
402
10:9
Bits
Default Value:
11
I/O Address:
8
7
6
®
6300ESB I/O Controller Hub
Lockable:
Device:
SMBus Wake Status
(SMB_WAK_STS)
TCOSCI_STS
PME_STS
Reserved
RI_STS
31
PMBASE + 28h
(ACPI PGPE0_BLK)
00000000h
No
Name
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when the PME# signal goes active.
Reserved.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when the RI# input signal goes active.
The SMBus controller may independently cause an SMI# or
SCI, so this bit does not need to do so (unlike the other bits in
this register).
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware to indicate that the wake event was
NOTE: This bit is set by the SMBus slave command 01h
NOTE: When SMB_WAK_STS is set due to SMBus slave
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when the TCO logic causes an SCI.
Additionally, when the PME_EN bit is set and the system
is in an S0 state, then the setting of the PME_STS bit will
generate an SCI or SMI# (when SCI_EN is not set).
When the PME_EN bit is set and the system is in an S1-
S4 state (or S5 state due to setting SLP_TYP and
SLP_EN), then the setting of the PME_STS bit will
generate a wake event, and an SCI (or SMI# if SMI_EN is
not set) will be generated. When the system is in an S5
state due to power button override, PME_STS will not
cause a wake event or SCI.
caused by the Intel
will be set by the WAKE/SMI# command type, even when
the system is already awake. The SMI handler should
then clear this bit.
(Wake/SMI#) even when the system is in the S0
state. Therefore, to avoid an instant wake on
subsequent transitions to sleep states, software must
clear this bit after each reception of the Wake/SMI#
command or just prior to entering the sleep state.
receiving a message, it will be cleared by internal logic
when a THRMTRIP# event happens or a Power Button
Override event. However, THRMTRIP# or Power
Button Override event will not clear SMB_WAK_STS
when it is set due to SMBALERT# signal going active.
®
Power Well:
Description
6300ESB ICH’s SMBus logic.This bit
Attribute:
Function:
Size:
0
Read/Write Clear
32-bit
Resume
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
R/WC
R/WC
R/WC
R/WC