NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 605

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

15—Intel
Multimedia Timer Registers
15.1
15.1.1
Table 528. Memory-Mapped Registers (Sheet 1 of 2)
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Memory Mapped Registers
The timer registers are memory mapped in a non-indexed scheme. This allows the
processor to directly access each register without having to use an index register. The
timer register space is 1024 bytes. The registers are generally aligned on 64-bit
boundaries to simplify implementation with IA64 processors. There are four possible
memory address ranges beginning at
1) FED0_0000h, 2) FED0_1000h, 3) FED0_2000h., 4) FED0_3000h. The choice of
address range will be selected by configuration bits in General Control register (offset
D0h) in Device 31, Function 0.
Behavioral Rules
000-007h
008-00Fh
010-017h
018-01Fh
020-027h
028-0EFh
0F0-0F7h
0F8-0FFh
100-107h
108-10Fh
110-11Fh
120-127h
128-12Fh
1. Software must not attempt to read or write across register boundaries. For
2. Software should not write to read-only registers.
3. Reads or writes to unimplemented timers should not be attempted. Timers 3:31
4. All registers are implemented in the Core Well, and all bits are reset by PXPCIRST#.
5. Reads to reserved registers or bits will return a value of ‘0’.
6. Software must not attempt locks to the memory mapped I/O ranges for Multimedia
example, a 32-bit access should be to offset x0h, x4h, x8h, or xCh. 32-bit accesses
should not be to 01h, 02h, 03h, 05h, 06h, 07h, 09h, 0Ah, 0Bh, 0Dh, 0Eh, or 0Fh.
Any accesses to these offsets will result in unexpected behavior and may result in a
master abort. However, these accesses will not result in system hangs. 64-bit
accesses may only be to x0h and must not cross 64-bit boundaries.
are not implemented.
Timers. When attempted, the lock is not honored, which means potential deadlock
conditions may occur.
Offset
General Capabilities and ID
Reserved
General Config
Reserved
General Interrupt Status
Reserved
Main Counter Value
Reserved
Timer 0 Config and Capabilities
Timer 0 Comparator Value
Reserved
Timer 1 Config and Capabilities
Timer 1 Comparator Value
Register
Intel
Read Only
Read-Write
Read/Write Clear
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
®
6300ESB I/O Controller Hub
Type
15
605
DS