NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 390

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8.8.1.6
Table 277. Offset C0h: MON_FWD_EN—IO Monitor Forward Enable Register (PM—
8.8.1.7
Intel
DS
390
Bits
Default Value:
3:0
7
6
5
4
®
6300ESB I/O Controller Hub
Lockable:
Note: Usage: Legacy Only.
Note: The Intel
Note: Usage: Legacy Only.
Device:
Offset:
MON7_FWD_EN
MON6_FWD_EN
MON5_FWD_EN
MON4_FWD_EN
Offset C0h: MON_FWD_EN—IO Monitor Forward Enable
Register
(PM—D31:F0)
LPC, independent of the POS_DEC_EN bit and the bits that enable the monitor to
generate an SMI#. The only criteria is that the address passes the decoding logic as
determined by the MON[n]_TRP_RNG and MON_TRP_MSK register settings.
D31:F0)
Offset C4h, C6h, C8h, CAh: MON[n]_TRP_RNG—I/O
Monitor [4:7]
Trap Range Register for Devices 4-7 (PM—D31:F0)
These registers set the ranges that Device Monitors 4-7 should trap. Offset C4h
corresponds to Monitor 4. Offset C6h corresponds to Monitor 5, etc.
When the trap is enabled in the MON_SMI register and the address is in the trap range
(and passes the mask set in the MON_TRP_MSK register) the Intel
generate an SMI#. This SMI# occurs when the address is positively decoded by
another device on PCI or by the Intel
LPC or some other Intel
point to registers in the Intel
is to be claimed by the Intel
6300ESB ICH internal registers (interrupt controller, RTC, etc.), the cycle will complete
Reserved
31
C0h
00h
No
Name
®
6300ESB ICH uses this register to enable the monitors to forward cycles to
0 = Disable. Cycles trapped by I/O Monitor 7 will not be
1 = Enable. Cycles trapped by I/O Monitor 7 will be forwarded
0 = Disable. Cycles trapped by I/O Monitor 6 will not be
1 = Enable. Cycles trapped by I/O Monitor 6 will be forwarded
0 = Disable. Cycles trapped by I/O Monitor 5 will not be
1 = Enable. Cycles trapped by I/O Monitor 5 will be forwarded
0 = Disable. Cycles trapped by I/O Monitor 4 will not be
1 = Enable. Cycles trapped by I/O Monitor 4 will be forwarded
Reserved.
forwarded to LPC.
to LPC.
forwarded to LPC.
to LPC.
forwarded to LPC.
to LPC.
forwarded to LPC.
to LPC.
®
6300ESB ICH internal registers). The trap ranges should not
®
®
6300ESB ICH and targets one of the permitted Intel
6300ESB ICH’s internal IDE, USB, AC’97. When the cycle
®
Power Well:
Description
6300ESB ICH (because it would be forwarded to
Attribute:
Function:
Size:
0
Read/Write
8-bit
Core
Order Number: 300641-004US
®
Intel
6300ESB ICH will
®
6300ESB ICH—8
November 2007
Access
R/W
R/W
R/W
R/W
®