NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 44

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Intel
DS
44
592 Offset 0E: HTYPE—Header Type ............................................................................... 660
593 Offset 18: BNUM—Bus Numbers ............................................................................... 661
594 Offset 1B: SLT—Secondary Latency Timer.................................................................. 661
595 Offset 1C: IOBL—I/O Base and Limit ......................................................................... 662
596 Offset 1E: SSTS—Secondary Status .......................................................................... 663
597 Offset 20: MBL—Memory Base and Limit.................................................................... 664
598 Offset 24: PMBL—Prefetchable Memory Base and Limit ................................................ 665
599 Offset 28: PMBU32—Prefetchable Memory Base Upper 32 Bits ...................................... 665
600 Offset 2C: PMLU32—Prefetchable Memory Limit Upper 32 Bits ...................................... 666
601 Offset 30: IOBLU16—I/O Base and Limit Upper 16 Bits ................................................ 666
602 Offset 34: CAPP—Capabilities List Pointer .................................................................. 667
603 Offset 3C: INTR—Interrupt Information ..................................................................... 667
604 Offset 3E: BCTRL—Bridge Control ............................................................................. 668
605 Offset 40: CNF—Intel® 6300ESB I/O Controller Hub Configuration................................ 671
606 Offset 42: MTT—Multi-Transaction Timer ................................................................... 673
607 Offset 44: STRP—PCI Strap Status............................................................................ 674
608 Offset 50: PX_CAPID—PCI-X Capabilities Identifier...................................................... 674
609 Offset 51: PX_NXTP—Next Item Pointer..................................................................... 674
610 Offset 52: PX_SSTS—PCI-X Secondary Status ............................................................ 675
611 Offset 54: PX_BSTS - PCI-X Bridge Status ................................................................. 676
612 Offset 58: PX_USTC - PCI-X Upstream Split Transaction Control ................................... 678
613 Offset 5C: PX_DSTC - PCI-X Downstream Split Transaction Control ............................... 679
614 Offset E0: ACNF – Additional Intel® 6300ESB ICH Configuration................................... 680
615 Offset E4: PCR - PCI Compensation Register .............................................................. 681
616 Offset F0: HCCR - Hub Interface Command/Control Register ........................................ 682
617 Offset F8h: PC33 - Prefetch Control – 33 MHz ............................................................ 683
618 Offset FAh: PC66 - Prefetch Control – 66 MHz ............................................................ 683
619 Intel
620 PCI-X Interface Command Encoding.......................................................................... 691
621 Intel
622 DEVSEL# Timing .................................................................................................... 692
623 Intel
624 Split Completion Messages....................................................................................... 693
625 Immediate Terminations of Completion Required Cycles to PCI/PCI-X ............................ 695
626 Immediate Terminations of Posted Write Cycles to PCI/PCI-X ....................................... 696
627 Split Terminations of Completion Required Cycles to PCI-X........................................... 696
628 Hub Interface Response to PCI-X Split Completion Terminations of Completion Required Cycles
629 Terminations of Completion Required Cycles to Hub Interface....................................... 698
630 Universal Asynchronous Receive And Transmit (UART0, UART1).................................... 704
631 Address Map .......................................................................................................... 706
632 Supported LPC Cycle Types ...................................................................................... 706
633 I/O Sync Bits Description......................................................................................... 707
634 UART Clock Divider Support ..................................................................................... 708
635 Baud Rate Examples ............................................................................................... 708
636 SIU Signal Reset States........................................................................................... 710
637 Internal Register Descriptions .................................................................................. 710
638 Receive Buffer Register (RBR) .................................................................................. 711
639 Transmit Holding Register (THR) .............................................................................. 711
640 Interrupt Enable Register (IER) ................................................................................ 712
641 Interrupt Conditions................................................................................................ 713
642 Interrupt Identification Register (IIR) ........................................................................ 713
643 Interrupt Identification Register Decode .................................................................... 714
644 FIFO Control Register (FCR) ..................................................................................... 714
645 Line Control Register (LCR) ...................................................................................... 716
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6300ESB I/O Controller Hub
697
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6300ESB I/O Controller Hub PCI Transactions ................................................... 684
6300ESB ICH Implementation of Requester Attribute Fields ................................ 692
6300ESB ICH Implementation Completer Attribute Fields ................................... 693
Intel
Order Number: 300641-004US
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6300ESB ICH—Contents
November 2007