NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 303

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

7—Intel
Table 170. Offset 3E - 3Fh: BRIDGE_CNT—Bridge Control Register (HUB-PCI—
November 2007
Order Number: 300641-004US
Bits
Default Value:
3
2
1
0
®
Device:
Offset:
6300ESB ICH
Parity Error Response
SERR# Enable
VGA Enable
ISA Enable
D30:F0)
(Sheet 3 of 3)
Enable
30
3E-3Fh
0000h
Name
0 = No VGA device on PCI.
1 = Indicates that the VGA device is on PCI. Therefore, the
The Intel
read/write for software compatibility. Since the Intel
6300ESB ICH forwards all I/O cycles that are not in the USB,
AC’97, or IDE ranges to PCI, this bit would have no effect.
ISA should be enabled on the legacy PCI or the PCI/PCI-X
bridge, but NOT both. If both are enabled, unpredictable
results will occur.
0 = Disable
1 = When this bit is set AND bit 8 in CMD register (D30:F0
NOTE: See
0 = Disable
1 = Enable the Hub Interface to PCI bridge for parity error
PCI to Hub Interface decoder will not accept memory
cycles in the range A0000h-BFFFFh. Note that the Intel
6300ESB ICH will never take I/O cycles in the VGA range
from PCI. If VGA is enabled on PCI-X Bridge Device 28
Function 0, offset 3Eh, bit 3. PCI-X will claim memory
cycles in the VGA range before the legacy PCI Bridge.
Offset 04h) is also set, the Intel
the SSE bit in PD_STS register (D30:F0, offset 06h, bit
14) and also generate an NMI (or SMI# if NMI routed to
SMI) when the SERR# signal is asserted. The internal
SERR# will be generated only if the SERR_EN bit is also
set in offset 04h.
detection and reporting on the PCI bus.
details on this bit.
®
6300ESB ICH ignores this bit. However, this bit is
Section 5.1.4, “SERR# Functionality”
Description
Attribute:
Function:
Size:
®
0
Read/Write
16-bit
6300ESB ICH will set
Intel
for more
®
®
6300ESB I/O Controller Hub
®
Access
R/W
R/W
R/W
R/W
303
DS