NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 743

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NHE6300ESB S L7XJ

Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet

Specifications of NHE6300ESB S L7XJ

Lead Free Status / RoHS Status
Compliant
20—Intel
20.1.7
20.1.8
November 2007
Order Number: 300641-004US
Bits
Bits
Default Value:
Default Value:
7:0
7:0
Table 667. Offset 0Bh: BCC—Base Class Code (SATA–D31:F2)
Table 668. Offset 0Dh: MLT—Master Latency Timer (SATA–D31:F2)
Device:
Device:
®
Offset:
Offset:
6300ESB ICH
Bus Master Latency
Base Class Code
Offset 0Bh: BCC—Base Class Code (SATA–D31:F2)
Offset 0Dh: MLT—Master Latency Timer (SATA–
D31:F2)
31
0Bh
01h
Name
31
0Dh
00h
Name
01 = Mass storage device
Hardwired to 00h. The IDE controller is implemented
internally, and is not arbitrated as a PCI device, so it does not
need a Master Latency Timer.
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
2
Read-Only
8-bit
2
Read-Only
8-bit
Intel
®
6300ESB I/O Controller Hub
Access
Access
RO
RO
743
DS

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