NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 528

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

12.1.2
12.1.3
Intel
DS
528
15:0
15:1
Bits
Bits
Default Value:
Default Value:
0
9
8
7
6
5
4
3
2
1
0
®
Table 426. Offset 02 - 03h: DID—Device Identification Register (SMBUS—
Table 427. Offset 04 - 05h: CMD—Command Register (SMBUS—D31:F3)
6300ESB I/O Controller Hub
I/O Space Enable (IOSE)
Device:
Device:
Offset:
Offset:
Postable Memory Write
Memory Space Enable
Parity Error Response
Special Cycle Enable
VGA Palette Snoop
Bus Master Enable
Fast Back-to-Back
Wait Cycle Control
Device ID value
Enable (PMWE)
SERR# Enable
Enable (FBE)
(SERREN)
Offset 02 - 03h: DID—Device Identification
Register (SMBUS—D31:F3)
D31:F3)
Offset 04 - 05h: CMD—Command Register
(SMBUS—D31:F3)
Reserved
(WCC)
31
02-03h
25A4h
Name
31
04-05h
0000h
Name
(BME)
(MSE)
(PER)
(VPS)
(SCE)
Reserved.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
Reserved as ‘0’.
0 = Disable
1 = Enables access to the SM Bus I/O space registers as
defined by the Base Address Register.
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
3
Read-Only
16-bit
3
Read-Only, Read/Write
16-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—12
November 2007
Access
Access
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO