NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 487

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

11—Intel
11.1.2
November 2007
Order Number: 300641-004US
10:9
Bits
Default Value:
3:0
15
14
13
12
11
8
7
6
5
4
Table 380. Offset 06 - 07h: Device Status
Device:
®
DEVSEL# Timing Status
Master Data Parity Error
Offset:
Signaled System Error
Received Master-Abort
Received Target Abort
Signaled Target-Abort
Detected Parity Error
UDF - User Definable
6300ESB ICH
Fast Back-to-Back
66 MHz Capable
Capabilities List
Status (RMA)
Status (RTA)
Status (STA)
Offset 06 - 07h: Device Status
Reserved
Detected
Features
Capable
(DEVT)
29
06 - 07h
0290h
Name
(DPE)
(SSE)
This bit is set by the Intel
error is seen on the internal interface to the USB host
controller due to a parity error on Hub Interface, regardless
of the setting of bit 6 or bit 8 in the Command register or any
other conditions. Software clears this bit by writing a ‘1’ to
this bit location. Note that the Parity Error Response bit in the
HL-to-PCI bridge should be set in order for the Hub Interface
parity errors to be forwarded to the USB2 interface. This is a
result of the point-to-point nature of the Hub Interface
0 = Software clears this bit by writing a ’1’ to this bit location.
1 = This bit is set by the Intel
0 = Software clears this bit by writing a ’1’ to this bit location.
1 = This bit is set when USB EHCI, as a master, receives a
0 = Software clears this bit by writing a ’1’ to this bit location.
1 = This bit is set when USB EHCI, as a master, receives a
This bit is used to indicate when the USB EHCI function
responds to a cycle with a target abort. There is no reason for
this to happen, so this bit will be hard-wired to ’0’.
This 2-bit field defines the timing for DEVSEL# assertion.
0 = Software clears this bit by writing a ’1’ to this bit location.
1 = This bit is set by the Intel
Reserved as 1.
Reserved as 0.
Reserved as 0.
This bit is hardwired to ‘1’ indicating the presence of a valid
capabilities pointer at offset 34h.
Reserved.
signals SERR# (internally). The SER_EN bit (bit 8 of the
Command Register) must be ’1’ for this bit to be set.
master-abort status on a memory access. This is treated
as a Host Error and halts the DMA engines. This event
may optionally generate an SERR# by setting the SERR#
Enable bit
target abort status on a memory access. This is treated
as a Host Error and halts the DMA engines. This event
may optionally generate an SERR# by setting the SERR#
Enable bit
data parity error is detected on a USB EHCI read
completion packet on the internal interface to the USB
EHCI host controller (due to an equivalent data parity
error on Hub Interface) and bit 6 of the Command
register is set to 1.
.
.
Description
®
Attribute:
Function:
6300ESB ICH whenever a parity
®
®
Size:
6300ESB ICH whenever it
6300ESB ICH whenever a
7
Read/ Write
16-bit
Intel
®
6300ESB I/O Controller Hub
Access
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
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