NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 572

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

13.2.7
13.2.8
Intel
DS
572
Bits
Default Value:
7:5
I/O Address:
4
3
2
1
0
®
Table 491. x_CR—Control Register
6300ESB I/O Controller Hub
Lockable:
Note: Software may read the registers at offsets 08h, 0Ah, and 0Bh by performing a 32-bit
Note: Reads across dWord boundaries are not supported.
Interrupt Enable (LVBIE)
Device:
Interrupt On Completion
Run/Pause Bus master
Reset Registers (RR)
FIFO Error Interrupt
Last Valid Buffer
Enable (IOCE)
Enable (FEIE)
x_CR—Control Register
read from address offset 08h. Software may also read this register individually by doing
a single 8-bit read to offset 0Bh. Reads across dWord boundaries are not supported.
GLOB_CNT—Global Control Register
Reserved
(RPBM)
31
NABMBAR + 0Bh (PICR), NABMBAR + 1Bh
(POCR), NABMBAR + 2Bh (MCCR), MBBAR
+ 4Bh (MC2CR), MBBAR + 5Bh (PI2CR),
MBBAR + 6Bh (SPCR)
00h
No
Name
Reserved.
This bit controls whether or not an interrupt occurs when a
buffer completes with the IOC bit set in its descriptor.
0 = Disable. Interrupt will not occur.
1 = Enable.
This bit controls whether the occurrence of a FIFO error will
cause an interrupt or not.
0 = Disable. Bit 4 in the Status Register will be set, but the
1 = Enable. Interrupt will occur.
This bit controls whether the completion of the last valid
buffer will cause an interrupt or not.
0 = Disable. Bit 2 in the Status register will still be set, but
1 = Enable.
0 = Removes reset condition.
1 = Contents of all Bus master related registers to be reset,
0 = Pause bus master operation. This results in all state
1 = Run. Bus master operation starts.
interrupt will not occur.
the interrupt will not occur.
except the interrupt enable bits (bit 4,3,2 of this
register). Software needs to set this bit but need not
clear it since the bit is self clearing. This bit must be set
only when the Run/Pause bit is cleared. Setting it when
the Run bit is set will cause undefined consequences.
information being retained (i.e., master mode operation
may be stopped and then resumed).
Description
Power Well:
Attribute:
Function:
Size:
5
Read/Write
8-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—13
November 2007
(special)
Access
R/W
R/W
R/W
R/W
R/W