NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 427

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
Table 315. Offset GPIOBASE + 04h: GP_IO_SEL—GPIO Input/Output Select
8.10.4
Table 316. Offset GPIOBASE + 0Ch: GP_LVL—GPIO Level for Input or Output
November 2007
Order Number: 300641-004US
9, 26
21:1
15:0
31:2
28:2
25:2
Bits
Bits
Default Value:
Default Value:
22
7,
6
4
Lockable:
Lockable:
®
Device:
Device:
Offset:
Offset:
6300ESB ICH
GP_LVL[n]
Register
Offset GPIOBASE + 0Ch: GP_LVL—GPIO Level for
Input or Output Register
Register
Reserved
Reserved
31
GPIOBASE +04h
0000FFFFh
No
Name
31
GPIOBASE +0Ch
1B3F0000h
No
Name
Reserved.
Always 0. The GPIOs are fixed as outputs.
Always 1. These GPIOs are fixed as inputs.
Reserved.
When GPIO[n] is programmed to be an output (through the
corresponding bit in the GP_IO_SEL register), the bit may be
updated by software to drive a high or low value on the
output pin. When GPIO[n] is programmed as an input,
software may read the bit to determine the level on the
corresponding input pin. These bits correspond to GPIO that
are in the Resume well, and will be reset to their default
values by RSMRST# and also by a write to the CF9h register.
0 = Low
1 = High
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Read-Only
32-bit
Resume
0
Read/Write
32-bit
See bit descriptions
Intel
®
6300ESB I/O Controller Hub
Access
Access
R/W
427
DS