NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 113

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.5.5.3
5.6
Table 41.
.
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Read Back Command
The Read Back command, written to port 43h, latches the count value, programmed
mode, and current states of the OUT pin and Null Count flag of the selected counter or
counters. The value of the counter and its status may then be read by I/O access to the
counter address.
The Read Back command may be used to latch multiple counter outputs at one time.
This single command is functionally equivalent to several counter latch commands, one
for each counter latched. Each counter's latched count is held until it is read or
reprogrammed. Once read, a counter is unlatched. The other counters remain latched
until they are read. When multiple count Read Back commands are issued to the same
counter without reading the count, all but the first are ignored.
The Read Back command may additionally be used to latch status information of
selected counters. The status of a counter is accessed by a read from that counter's I/
O port address. When multiple counter status latch operations are performed without
reading the status, all but the first are ignored.
Both count and status of the selected counters may be latched simultaneously. This is
functionally the same as issuing two consecutive, separate Read Back commands.
When multiple count and/or status Read Back commands are issued to the same
counters without any intervening reads, all but the first are ignored.
When both count and status of a counter are latched, the first read operation from that
counter will return the latched status, regardless of which was latched first. The next
one or two reads, depending on whether the counter is programmed for one or two
type counts, return the latched count. Subsequent reads return unlatched count.
8259 Interrupt Controllers (PIC) (D31:F0)
The Intel
that provide system interrupts for the ISA compatible interrupts. These interrupts are:
system timer, keyboard controller, serial ports, parallel ports, floppy disk, IDE, mouse,
and DMA channels. In addition, this interrupt controller may support the PCI based
interrupts, by mapping the PCI interrupt onto the compatible ISA interrupt line. Each
8259 core supports eight interrupts, numbered zero through seven.
how the cores are connected.
Interrupt Controller Core Connections (Sheet 1 of 2)
Master
8259
®
6300ESB ICH incorporates the functionality of two 8259 interrupt controllers
Input
8259
0
1
2
3
4
5
6
7
Internal
Keyboard
Internal
Serial Port A
Serial Port B
Parallel Port / Generic
Floppy Disk
Parallel Port / Generic
Typical Interrupt
Source
Internal Timer / Counter 0 output / MMT #0
IRQ1 via SERIRQ
Slave Controller INTR output
IRQ3 via SERIRQ, PIRQx
IRQ4 via SERIRQ, PIRQx
IRQ5 via SERIRQ, PIRQx
IRQ6 via SERIRQ PIRQx,
IRQ7 via SERIRQ PIRQx,
Connected Pin / Function
Intel
®
6300ESB I/O Controller Hub
Table 41
shows
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