NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 363

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
8.4.4
Table 240. ICW3—Master Controller Initialization Command Word 3 Register
8.4.5
Table 241. ICW3—Slave Controller Initialization Command Word 3 Register
November 2007
Order Number: 300641-004US
Bits
Bits
Default Value:
Default Value:
7:3
1:0
7:3
2:0
2
®
Slave Identification Code
Device:
Device:
Offset:
Offset:
6300ESB ICH
Cascaded Interrupt
Controller IRQ
Connection
ICW3—Master Controller Initialization Command
Word 3 Register
ICW3—Slave Controller Initialization Command
Word 3 Register
31
21h
All bits undefined
Name
31
A1h
All bits undefined
Name
0 = These bits must be programmed to zero.
This bit indicates that the slave controller is cascaded on
IRQ2. When IRQ8#-IRQ15 is asserted, it goes through the
slave controller’s priority resolver. The slave controller’s INTR
output onto IRQ2. IRQ2 then goes through the master
controller’s priority solver. When it wins, the INTR signal is
asserted to the processor and the returning interrupt
acknowledge returns the interrupt vector for the slave
controller.
1 = This bit must always be programmed to a 1.
0 = These bits must be programmed to zero.
0 = These bits must be programmed to zero.
These bits are compared against the slave identification code
broadcast by the master controller from the trailing edge of
the first internal INTA# pulse to the trailing edge of the
second internal INTA# pulse. These bits must be programmed
to 02h to match the code broadcast by the master controller.
When 02h is broadcast by the master controller during the
INTA# sequence, the slave controller assumes responsibility
for broadcasting the interrupt vector.
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Write-Only
8-bit
0
Write-Only
8-bit
Intel
®
6300ESB I/O Controller Hub
Access
Access
WO
WO
363
DS