NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 200

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 88.
Table 89.
Intel
DS
200
®
6300ESB I/O Controller Hub
TD Control and Status (Sheet 3 of 3)
TD Token
15:11
31:21
18:15
10:0
14:8
7:0
Bit
Bit
16
20
19
Bus Turn Around Time-out (BTTO):
1 = This bit is set to a 1 by the Intel
Reserved
Actual Length (ACTLEN): The Actual Length field is written by the Intel
ICH at the conclusion of a USB transaction to indicate the actual number of bytes that
were transferred. It may be used by the software to maintain data integrity. The value
programmed in this register is encoded as n-1 (see Maximum Length field description in
the TD Token).
Maximum Length (MAXLEN): The Maximum Length field specifies the maximum
number of data bytes allowed for the transfer. The Maximum Length value does not
include protocol bytes, such as Packet ID (PID) and CRC. The maximum data packet is
1280 bytes. The 1280 packet length is the longest packet theoretically ensured to fit
into a frame. Actual packet maximum lengths are set by HCD according to the type and
speed of the transfer. Note that the maximum length allowed by the USB specification
is 1023 bytes. The valid encodings for this field are:
0x000 = 1 byte
0x001 = 2 bytes
....
0x3FE = 1023 bytes
0x3FF = 1024 bytes
....
0x4FF = 1280 bytes
0x7FF = 0 bytes (null data packet)
Note that values from 500h to 7FEh are illegal and cause a consistency check failure.
In the transmit case, the Intel
the number of bytes it fetches from host memory. In most cases, this is the number of
bytes it will actually transmit. In rare cases, the Intel
access memory (e.g., due to excessive latency) in time to avoid underrunning the
Reserved.
Data Toggle (D): This bit is used to synchronize data transfers between a USB
endpoint and the host. This bit determines which data PID is sent or expected
(0=DATA0 and 1=DATA1). The Data Toggle bit provides a 1-bit sequence number to
check whether the previous packet completed. This bit must always be 0 for
Isochronous TDs.
Endpoint (ENDPT): This 4-bit field extends the addressing internal to a particular
device by providing 16 endpoints. This permits more flexible addressing of devices in
which more than one sub-channel is required.
Device Address: This field identifies the specific device serving as the data source or
sink.
Packet Identification (PID): This field contains the Packet ID to be used for this
transaction. Only the IN (69h), OUT (E1h), and SETUP (2Dh) tokens are allowed. Any
other value in this field causes a consistency check failure resulting in an immediate
halt of the Intel
that a bus time-out condition was detected for this USB transaction. This time-out
is specially defined as not detecting an IDLE-to ‘K’ state Start of Packet (SOP)
transition from 16 to 18 bit times after the SE0-to-IDE transition of previous End of
Packet (EOP).
®
6300ESB ICH. Bits [3:0] are complements of bits [7:4].
®
6300ESB ICH uses this value as a terminal count for
®
Description
Description
6300ESB ICH during status updates to indicate
®
6300ESB ICH may be unable to
Order Number: 300641-004US
Intel
®
6300ESB ICH—5
®
November 2007
6300ESB