NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 583

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

14—Intel
14.1.3
Table 499. Offset 04 - 05h: PCICMD—PCI Command Register (Modem—D31:F6)
November 2007
Order Number: 300641-004US
15:1
Bits
Default Value:
0
9
8
7
6
5
4
3
2
1
0
Lockable:
Note: PCICMD is a 16-bit control register. Refer to the PCI 2.2 specification for complete
Device:
Invalidate Enable (MWI)
®
Offset:
Parity Error Response
SERR# Enable (SEN)
Special Cycle Enable
6300ESB ICH
Memory Space (MS)
VGA Palette Snoop
Wait Cycle Control
Memory Write and
Bus Master Enable
Fast Back-to-Back
I/O Space (IOS)
Enable (FBE)
Offset 04 - 05h: PCICMD—PCI Command Register
(Modem—D31:F6)
details on each bit.PCISTA—Device Status Register (Modem—D31:F6).
Reserved
(WCC)
31
04 - 05h
0000h
No
Name
(BME)
(PER)
(VPS)
(SCE)
Reserved. Read 0.
Not implemented. Hardwired to ‘0’.
Not implemented. Hardwired to ‘0’.
Not implemented. Hardwired to ‘0’.
Not implemented. Hardwired to ‘0’.
Not implemented. Hardwired to ‘0’.
Not implemented. Hardwired to ‘0’.
Not implemented. Hardwired to ‘0’.
Controls standard PCI bus mastering capabilities.
0 = Disable
1 = Enable
Hardwired to ‘0’; AC ‘97 does not respond to memory
accesses.
This bit controls access to the I/O space registers.
0 = Disable access (default = 0).
1 = Enable access to I/O space. The Native PCI Mode Base
Address register should be programmed prior to setting
this bit.
Power Well:
Description
Attribute:
Function:
Size:
6
Read-Only
16-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
R/W
R/W
583
DS