NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 349

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
8.2.2
Table 221. DMABASE_CC—DMA Base and Current Count Registers
November 2007
Order Number: 300641-004US
15:0
Bits
Default Value:
I/O Address:
Lockable:
®
Device:
Base and Current Count
6300ESB ICH
DMABASE_CC—DMA Base and Current Count
Registers
31
Ch. #0 = 01h; Ch. #1 =
03h, Ch. #2 = 05h; Ch.
#3 = 07h, Ch. #5 = C6h
Ch. #6 = CAh, Ch. #7 =
CEh
Undefined
No
Name
This register determines the number of transfers to be
performed. The address specified points to two separate
registers. On writes, the value is stored in the Base Count
register and copied to the Current Count register. On reads,
the value is returned from the Current Count register.
The actual number of transfers is one more than the number
programmed in the Base Count Register (i.e., programming a
count of 4h results in 5 transfers). The count is decrements in
the Current Count register after each transfer. When the
value in the register rolls from zero to FFFFh, a terminal count
is generated. When the channel is in auto-initialize mode, the
Current Count register will be reloaded from the Base Count
register after a terminal count is generated.
For transfers to/from an 8-bit slave (channels 0-3), the count
register indicates the number of bytes to be transferred. For
transfers to/from a 16-bit slave (channels 5-7), the count
register indicates the number of words to be transferred.
The register is accessed in 8 bit quantities. The byte is
pointed to by the current byte pointer flip/flop. Before
accessing a count register, the byte pointer flip/flop should be
cleared to ensure that the low byte is accessed first.
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write
16-bit, accessed in two 8-bit quantities
Core
Intel
®
6300ESB I/O Controller Hub
Access
R/W
349
DS