NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 142

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 59.
5.10.1.3 FERR#/IGNNE# (Coprocessor Error)
Figure 14. Coprocessor Error Timing Diagram
Intel
DS
142
®
6300ESB I/O Controller Hub
INIT# Going Active (Sheet 2 of 2)
The Intel
IGNNE# pins. The function is enabled through the COPROC_ERR_EN bit (Device
31:Function 0, Offset D0, bit 13). FERR# is tied directly to the Coprocessor Error signal
of the processor. When FERR# is driven active by the processor, IRQ13 goes active
(internally). When it detects a write to the COPROC_ERR register, the Intel
ICH negates the internal IRQ13 and drives IGNNE# active. IGNNE# remains active
until FERR# is driven inactive. IGNNE# is never driven active unless FERR# is active.
When COPROC_ERR_EN is not set, the assertion of FERR# will have not generate an
internal IRQ13, nor will the write to F0h generate IGNNE#.
PORTCF9 write, where RST_CPU (bit 2) was a 0 and
SYS_RST(bit 1) transitions from 0 to 1.
RCIN# input signal goes low. RCIN# is expected to
be driven by the external microcontroller (KBC).
CPU BIST
I/O Write to F0h
Internal IRQ13
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Cause of INIT# Going Active
6300ESB ICH supports the coprocessor error function with the FERR#/
FERR#
IGNNE#
0 to 1 transition on RCIN# must occur
before the Intel
INIT# to be generated again.
NOTE: RCIN# signal is expected to be
In order to enter BIST, the software sets
CPU_BIST_EN bit and then does a full
processor reset using the CF9 register.
high during S1-M and low during
S3, S4, and S5 states. Transition
on the RCIN# signal in those
states (or the transition to those
states) may not necessarily cause
the INIT# signal to be generated
to the processor
®
Comment
Order Number: 300641-004US
6300ESB ICH will arm
Intel
®
6300ESB ICH—5
®
November 2007
6300ESB