NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 394

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8.8.3.1
Table 284. PM1_STS—Power Management 1 Status Register (Sheet 1 of 2)
Intel
DS
394
14:1
Bits
Default Value:
15
11
I/O Address:
2
®
6300ESB I/O Controller Hub
Lockable:
Note: Usage: ACPI or Legacy
Note: When bit 10 or 8 in this register is set, and the corresponding _EN bit is set in the
Note: Bit 5 does not cause an SMI# or a wake event. Bit 0 does not cause a wake event but
Device:
WAK_STS: Wake Status
Button Override Status
PRBTNOR_STS: Power
PM1_STS—Power Management 1 Status Register
PM1_EN register, the Intel
S0 state (or if already in an S0 state when the event occurs), the Intel
will also generate an SCI when the SCI_EN bit is set, or an SMI# when the SCI_EN bit
is not set.
may cause an SMI# or SCI.
Reserved
31
PMBASE + 00h
(ACPI PM1a_EVT_BLK)
0000h
No
Name
This bit is not affected by hard resets caused by a CF9 write,
but is reset by RSMRST#.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when the system is in one of the sleep
When the AFTERG3_EN bit is not set and a power failure
(such as removed batteries) occurs without the SLP_EN bit
set, the system will return to an S0 state when power
returns, and the WAK_STS bit will not be set.
When the AFTERG3_EN bit is set and a power failure occurs
without the SLP_EN bit having been set, the system will go
into an S5 state when power returns, and a subsequent wake
event will cause the WAK_STS bit to be set. Note that any
subsequent wake event would have to be caused by either a
Power Button press, or an enabled wake event that was
preserved through the power failure (enable bit in the RTC
well).
Reserved.
This bit is set any time a Power Button Override occurs (I.E.
the power button is pressed for at least four consecutive
seconds), or due to the corresponding bit in the SMBus slave
message. The power button override causes an unconditional
transition to the S5 state, as well as sets the AFTERG3 bit.
The BIOS or SCI handler clears this bit by writing a 1 to it.
This bit is not affected by hard resets through CF9h writes,
and is not reset by RSMRST#. Thus, this bit is preserved
through power failures.
states (through the SLP_EN bit) and an enabled wake
event occurs. Upon setting this bit, the Intel
ICH will transition the system to the ON state.
®
6300ESB ICH will generate a Wake Event. Once back in an
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write Clear
16-bit
Bits 0-7: Core;
Bits 8-10, 12-15;Resume;
Bit 11: RTC
®
6300ESB
Order Number: 300641-004US
Intel
®
®
6300ESB ICH—8
6300ESB ICH
November 2007
Access
R/WC
R/WC