NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 509

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

11—Intel
11.2.2.1 Offset CAPLENGTH + 00 - 03h: USB EHCI CMD—USB
Table 412. Offset CAPLENGTH + 00 - 03h: USB EHCI CMD—USB EHCI Command
November 2007
Order Number: 300641-004US
31:2
23:1
15:8
11:8
Bits
Default Value:
4
6
7
6
5
Device:
®
Offset:
Asynchronous Schedule
Light Host Controller
6300ESB ICH
Interrupt Threshold
Asynchronous Park
Interrupt on Async
Advance Doorbell
Unimplemented
EHCI Command Register
Register (Sheet 1 of 3)
Mode Bits
Reserved
Reserved
Control
Enable
29
CAPLENGTH + 00-03h
00080000h
Name
Reset
Reserved. These bits are reserved and should be set to ’0’.
Default 04h. This field is used by system software to select
the maximum rate at which the host controller will issue
interrupts. The only valid values are defined below. When
software writes an invalid value to this register, the results
are undefined.
Reserved. These bits are reserved and should be set to ’0’.
This field is hardwired to 000b because the host controller
does not support this optional feature.
The Intel
reset and hardwires this bit to 0.
This bit is used as a doorbell by software to tell the host
controller to issue an interrupt the next time it advances
asynchronous schedule. Software must write a ’1’ to this bit
to ring the doorbell. When the host controller has evicted all
appropriate cached schedule state, it sets the Interrupt on
Async Advance status bit in the USBSTS register. When the
Interrupt on Async Advance Enable bit in the USBINTR
register is a ’1’, the host controller will assert an interrupt at
the next interrupt threshold. See the EHCI specification for
operational details.
The host controller sets this bit to a ’0’ after it has set the
Interrupt on Async Advance status bit in the USBSTS register
to a ’1’.
Software should not write a ’1 ’to this bit when the
asynchronous schedule is inactive. Doing so will yield
undefined results.
Default 0b. This bit controls whether the host controller skips
processing the Asynchronous Schedule. Values mean:
0 = Do not process the Asynchronous Schedule
1 = Use the ASYNCLISTADDR register to access the
Value
00h
01h
02h
04h
08h
10h
20h
40h
Asynchronous Schedule.
®
6300ESB ICH does not implement this optional
Maximum Interrupt Interval
Reserved
1 micro-frame
2 micro-frames
4 micro-frames
8 micro-frames (default, equates to 1 ms)
16 micro-frames (2 ms)
32 micro-frames (4 ms)
64 micro-frames (8 ms)
Description
Attribute:
Function:
Size:
7
Read/Write
32-bit
Intel
®
6300ESB I/O Controller Hub
Access
R/W
R/W
R/W
RO
509
DS