NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 682

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18.6.1.33Offset F0: HCCR - Hub Interface Command/Control
18.6.1.34Offset F8h – Offset FFh: Prefetch Control Registers
Intel
DS
682
31:2
19:1
15:1
09:0
07:0
03:0
Bits
5:4
00
0
6
0
8
6
1
®
Table 616. Offset F0: HCCR - Hub Interface Command/Control Register
6300ESB I/O Controller Hub
Device
Maximum
Data Size
Offset
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
(MAXD)
Name
Register
The following registers contain prefetch parameters. Each parameter is in 64 byte
cache line quantities. BIOS programs the values in these registers upon power up. The
values in this register are zero-based – a zero means 64 bytes, and ’1’ means 128
bytes, etc.
There is a fifth parameter in the prefetch algorithm, called “D”, which is the delay to
wait before sending a subsequent request of RS when prior requests of RS still have not
brought the prefetch buffers above TS. Its value is in PCI clocks, and is [RS]:111. For
example, when RS = ‘0101’b, then D is ‘0101111’b.
Note that for Memory Read (MR) and Memory Read Line (MRL) commands in PCI, no
prefetching is done. A fetch of one cache line (based upon the cache line size register)
is performed and when it drains, the delayed transaction is complete. A new delayed
transaction is established when the master wished the burst to continue.
28
F0
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
This field specifies the maximum size write a master should
request in a single burst, as well as the maximum optimal
size read completion a target should return. Encoding:
000: 32 Bytes
Others: 64 Bytes
Reserved.
Description
Attribute:
Function
Size:
0
Read/Write
32-bit
Order Number: 300641-004US
Reset
Value
000
Intel
0h
00
0
0
0
0
0
®
6300ESB ICH—18
November 2007
Access
R/W
R/W
RO
RO
RO
RO
RO
R