NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 297

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

7—Intel
Table 163. Offset 20 - 21h: MEMBASE—Memory Base Register (HUB-PCI—D30:F0)
7.1.18
Table 164. Offset 22 - 23h: MEMLIM—Memory Limit Register (HUB-PCI—D30:F0)
November 2007
Order Number: 300641-004US
15:4
15:4
Bits
Bits
Default Value:
Default Value:
3:0
3:0
®
Device:
Device:
Offset:
Offset:
6300ESB ICH
Memory Address Base
Memory Address Limit
Offset 22 - 23h: MEMLIM—Memory Limit Register
(HUB-PCI—D30:F0)
This register defines the upper limit of the Hub Interface to PCI non-prefetchable
memory range. Since the Intel
accesses to PCI, the Intel
when not to accept cycles as a target.
This register must be initialized by the configuration software. For the purpose of
address decode, address bits AD[19:0] are assumed to be FFFFFh. Thus, the top of the
defined memory address range will be aligned to a 1 Mbyte boundary.
Reserved
Reserved
30
20-21h
FFF0h
Name
30
22-23h
0000h
Name
Defines the base of the memory range for PCI. These 12 bits
correspond to address bits 31:20.
Reserved.
Defines the top of the memory range for PCI. These 12 bits
correspond to address bits 31:20.
Reserved.
®
6300ESB ICH will only use this information for determining
®
6300ESB ICH will forward all Hub Interface memory
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Read/Write
16-bit
0
Read/Write
16-bit
Intel
®
6300ESB I/O Controller Hub
Access
Access
R/W
R/W
297
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