NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 301

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

7—Intel
7.1.24
Table 170. Offset 3E - 3Fh: BRIDGE_CNT—Bridge Control Register (HUB-PCI—
November 2007
Order Number: 300641-004US
15:1
Bits
Default Value:
12
11
10
1
9
8
7
®
Fast Back to Back Enable
Device:
PERR# to SERR# Enable
Offset:
6300ESB ICH
Discard Timer SERR#
Discard Timer Status
Secondary Discard
Primary Discard
Enable (DTSE)
Timer (PDT)
Timer (SDT)
Offset 3E - 3Fh: BRIDGE_CNT—Bridge Control
Register (HUB-PCI—D30:F0)
D30:F0)
Reserved
(Sheet 1 of 3)
30
3E-3Fh
0000h
Name
(DTS)
Reserved.
When this bit is set to ‘1’ PCI PERR NMI reporting is enabled.
In addition to setting this bit, you also must set bit 1 of
D30_F0 PNE Register.
When this bit is set to a ‘1’ and PERR# is asserted on PCI, the
PERR# Assertion detect status bit (in the Secondary Status
Register) will indicate a PERR# internal SERR# assertion. The
SERR# can be a s source on NMI.
Controls the generation of SERR# on the primary interface in
response to a timer discard on the secondary interface:
This bit replaces bit 1 of offset 90h, which held this function in
ICH3.
This bit is set to a ‘1’ when the secondary discard timer
expires (there is no discard timer for the primary interface).
This bit replaces bit 1 of offset 92h, which held this function in
ICH3.
Sets the maximum number of PCI clock cycles that the Intel
6300ESB ICH waits for an initiator on PCI to repeat a delayed
transaction request. The counter starts once the delayed
transaction completion is at the head of the queue. When the
master has not repeated the transaction at least once before
the counter expires, the Intel
transaction from its queue.
This bit is RW for software compatibility only.
Hardwired to ‘0’. The PCI logic will not generate fast back-to-
back cycles on the PCI bus.
• When ‘0’: Do not generate SERR# on a secondary timer
• When ‘1’: Generate SERR# in response to a secondary
• When ‘0’: The PCI master timeout value is between 2
• When ‘1’: The PCI master timeout value is between 2
discard
timer discard.
and 2
and 2
16
11
PCI clocks
PCI clocks
Section 7.1.28
Description
Attribute:
Function:
®
Size:
6300ESB ICH discards the
0
Read/Write
16-bit
Intel
®
6300ESB I/O Controller Hub
15
10
®
Access
R/W
R/W
R/W
R/W
RW
301
DS