NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 495

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

11—Intel
Table 395. Offset 54 - 55h: Power Management Control/Status
11.1.18 Offset 58h: Debug Port Capability ID
Table 396. Offset 58h: Debug Port Capability ID
November 2007
Order Number: 300641-004US
NOTE: Reset (bits 15, 8): suspend well, and not D3-to-D0 warm reset nor core well reset.
Bits
Bits
Default Value:
Default Value:
7:2
1:0
7:0
Device:
Device:
Debug Port Capability ID
®
Offset:
Offset:
6300ESB ICH
PowerState
Reserved
29
54 - 55h
0000h
Name
29
58h
0Ah
Name
Reserved.
This 2-bit field is used both to determine the current power
state of EHC function and to set a new power state. The
definition of the field values are:
00b – D0 state
11b – D3 hot state
When software attempts to write a value of 10b or 01b in to
this field, the write operation must complete normally;
however, the data is discarded and no state change occurs.
When in the D3 hot state, the Intel
accept accesses to the EHC memory range, but the
configuration space must still be accessible. When not in the
D0 state, the generation of the interrupt output is blocked.
Specifically, the PIRQ[H] is not asserted by the Intel
6300ESB ICH when not in the D0 state.
When software changes this value from the D3hot state to
the D0 state, an internal warm (soft) reset is generated, and
software must re-initialize the function.
This register is hardwired to 0Ah, which indicates that this is
the start of a Debug Port Capability structure.
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
®
7
Read/Write
16-bit
7
Read-Only
8-bit
6300ESB ICH must not
Intel
®
®
6300ESB I/O Controller Hub
Access
Access
R/W
RO
495
DS