NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 74

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 20.
3.19
Intel
DS
74
®
6300ESB I/O Controller Hub
Note: Alternative signal definition is for pin strap selected feature muxing. GPIOs muxing is
Universal Asynchronous Receive and Transmit (UART0, 1) (Sheet 2 of
2)
General Purpose I/O
based on GPIO configurations.
Signal Name
SIU0_DTR#
SIU1_DTR#
SIU0_RTS#
SIU1_RTS#
SIU0_DCD
SIU1_DCD
SIU0_DSR
SIU1_DSR
SIU0_RI#
SIU1_RI#
Type
O
O
I
I
I
DATA SET READY for UART 0, 1: Active low, this pin indicates that
the external agent is ready to communicate with the Intel
ICH UARTS. These pins have no effect on the transmitter.
NOTE: These pins could be used as Modem Status Input whose
DATA CARRIER DETECT for UART 0, 1: Active low, this pin indicates
that data carrier has been detected by the external agent.
NOTE: These pins are Modem Status Input whose condition may be
RING INDICATOR for UART 0, 1: Active low, this pin indicates that a
telephone ringing signal has been received by the external agent.
NOTE: These pins are Modem Status Input whose condition may be
DATA TERMINAL READY for UART 0, 1: When low these pins
informs the modem or data set that the Intel
are ready to establish a communication link. The DTR#x(x=0,1) output
signals may be set to an active low by programming the DTRx (x-0,1)
(bit0) of the Modem control register to a logic ‘1’. A Reset operation
sets this signal to its inactive state (logic ‘1’). LOOP mode operation
holds this signal in its inactive state.
REQUEST TO SEND for UART 0, 1: When low these pins informs the
modem or data set that the Intel
establish a communication link. The RTS#x, where x = 0,1, output
signals may be set to an active low by programming the RTS#x (bit1)
of the Modem control register to a logic ‘1’. A Reset operation sets this
signal to its inactive state (logic ‘1’). LOOP mode operation holds this
signal in its inactive state.
condition may be tested by the processor by reading bit 5
(DSR) of the Modem Status register. Bit 5 is the complement of
the DSR# signal. Bit 1 (DDSR) of the Modem status register
(MSR) indicates whether the DSR# input has changed state
since the previous reading of the MSR. When the DSR bit of the
MSR changes state, an interrupt is generated when the Modem
Status Interrupt is enabled.
tested by the processor by reading bit 7 (DCD) of the Modem
Status register (MSR). Bit 7 is the complement of the DCD#
signal. Bit 3 (DDCD) of the MSR indicates whether the DCD#
input has changed state since the previous reading of the MSR.
When the DCD bit of the MSR changes state, an interrupt is
generated when the Modem Status Interrupt is enabled.
tested by the processor by reading bit 6 (RI) of the Modem
Status register (MSR). Bit 6 is the complement of the RI#
signal. Bit 2 (TERI) of the MSR indicates whether the RI# input
has transitioned back to an inactive state. When the RI bit of
the MSR changes from a 1 to 0, an interrupt is generated when
the Modem Status Interrupt is enabled.
Description
®
6300ESB ICH UART 0, 1are ready to
®
Order Number: 300641-004US
6300ESB ICH UART 0, 1
Intel
®
6300ESB ICH—3
®
November 2007
6300ESB