NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 229

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.18.8.2 Suspend Feature
5.18.8.3 ACPI Device States
5.18.8.4 ACPI System States
5.18.8.5 Low-power system Considerations
November 2007
Order Number: 300641-004US
®
6300ESB ICH
The EHCI Specification describes the details of Port Suspend and Resume in detail in
Section 4.3.
The USB EHCI function only supports the D0 and D3 PCI Power Management states.
Notes regarding the Intel
The EHC behavior as it relates to other power management states in the system is
summarized in the following list:
The Intel
power configurations. However, some features may be especially useful for the low
power configurations.
1. The EHC hardware does not inherently consume any more power when it is in the
2. In the D0 state, all implemented EHC features are enabled.
3. In the D3 state, accesses to the EHC memory-mapped I/O range will master abort.
4. In the D3 state, the EHC interrupt must never assert for any reason. The internal
5. When the Device Power State field is written to D0 from D3, an internal reset is
6. Attempts to write any other value into the Device Power State field other than 00b
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D0 state than it does in the D3 state. However, software is required to suspend or
disable all ports prior to entering the D3 state such that the maximum power
consumption is reduced.
Note that, since the Debug Port uses the same memory range, the Debug Port is
only operational when the EHC is in the D0 state.
PME# signal is used to signal wake events, etc.
generated. See section EHC Resets for general rules on the effects of this reset.
(D0 state) and 11b (D3 state) will complete normally without changing the current
value in this field. See
Control/Status”
The System is always in the S0 state when the EHC is in the D0 state. However,
when the EHC is in the D3 state, the system may be in any power management
state (including S0).
When in D0, the Pause feature (See
dynamic processor low-power states to be entered.
All core well logic is reset in the S3/S4/S5 states (core power turns off).
Low-power systems are not likely to use all four of the USB ports that are provided
on the Intel
mechanisms for changing the structural parameters of the EHC and hiding unused
USB UHCI controllers. See Intel
should configure the Intel
Low-power systems may want to minimize the conditions that will wake the
system. The Intel
Status and Control registers, as specified in the EHCI spec, for this purpose.
Low-power systems may want to cut suspend well power to some or all USB ports
when in a low-power state. The Intel
Wake Capability Register in the EHC Configuration Space for this platform-specific
information to be communicated to software.
®
6300ESB ICH USB EHCI implementation does not behave differently in low
®
6300ESB ICH. With this in mind, the Intel
for information regarding offset 54h, bits [1:0].
®
6300ESB ICH implements the “Wake Enable” bits in the Port
®
Section 11.1.17, “Offset 54 - 55h: Power Management
6300ESB ICH implementation of the Device States:
®
6300ESB ICH.
®
6300ESB ICH BIOS Specification on how BIOS
Section 5.18.8.1, “Pause
®
6300ESB ICH implements the optional Port
®
Intel
6300ESB ICH provides
®
6300ESB I/O Controller Hub
Feature”) enables
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