NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 395

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
Table 284. PM1_STS—Power Management 1 Status Register (Sheet 2 of 2)
November 2007
Order Number: 300641-004US
Bits
Default Value:
7:6
4:1
10
I/O Address:
9
8
5
0
Lockable:
®
GBL _STS: Global Status
Device:
6300ESB ICH
PWRBTN__STS: Power
RTC_STS: RTC Status
TMROF_STS: Timer
Overflow Status
Button Status
Reserved
Reserved
Reserved
31
PMBASE + 00h
(ACPI PM1a_EVT_BLK)
0000h
No
Name
This bit is not affected by hard resets caused by a CF9 write,
but is reset by RSMRST#.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when the RTC generates an alarm
Reserved.
This bit is not affected by hard resets caused by a CF9 write.
0 = When the PWRBTN# signal is held low for more than four
1 = This bit is set when the PWRBTN# signal is asserted
Reserved.
0 = The SCI handler should then clear this bit by writing a 1
1 = Set when an SCI is generated due to BIOS wanting the
Reserved.
0 = The SCI or SMI# handler clears this bit by writing a 1 to
1 = This bit gets set any time bit 22 of the 24-bit timer goes
(assertion of the IRQ8# signal). Additionally when the
RTC_EN bit is set, the setting of the RTC_STS bit will
generate a wake event.
seconds, the hardware clears the PWRBTN_STS bit, sets
the PWRBTNOR_STS bit, and the system transitions to
the S5 state with only PWRBTN# enabled as a wake
event. This bit may be cleared by software by writing a
one to the bit position.
(low), independent of any other enable bit. See
PWRBTN_EN for the effect when PWRBTN_STS goes
active. PWRBTN_STS is always a wake event. This bit is
only set by hardware and can be cleared by software
writing a one to this bit position. This bit is not affected
by hard resets caused by a CF9 write, but is reset by
RSMRST#.
to the bit location.
attention of the SCI handler. BIOS has a corresponding
bit, BIOS_RLS, which will cause an SCI and set this bit.
the bit location.
high (bits are numbered from 0 to 23). This will occur
every 2.3435 seconds. When the TMROF_EN bit is set,
then the setting of the TMROF_STS bit will additionally
generate an SCI or SMI# (depending on the SCI_EN).
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write Clear
16-bit
Bits 0-7: Core;
Bits 8-10, 12-15;Resume;
Bit 11: RTC
Intel
®
6300ESB I/O Controller Hub
Access
R/WC
R/WC
R/WC
R/WC
395
DS