NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 275

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

6—Intel
Register and Memory Mapping
6.1
November 2007
Order Number: 300641-004US
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6300ESB ICH
The Intel
space, memory space and sets of PCI configuration registers that are located in PCI
configuration space. This chapter details the Intel
maps. Register access is also described.
Register-level address maps and Individual register bit descriptions are provided in the
following chapters. The following notations are used in the chapters that follow.
RO
WO
R/W
R/WC
Default
PCI Devices and Functions
The Intel
These functions are divided into four PCI devices. The first is the Hub Interface Link-To-
PCI bridge, D: 30 F:0. The second device, D31:F1, contains most of the standard PCI
functions present in most ICHs, as well as some new related Intel
features; SATA and SMBus Controller. The third device, D29 Fx, is the USB host
controller device which includes new features specific to the Intel
Watchdog Timer and an additional IOxAPIC. The fourth PCI device, D28:F0, is also a
new Intel
When a particular system does not want to support any one of Device 31’s, 29’s or 28’s
functions, they may individually be disabled. When a function is disabled, it does not
appear at all to the software. A disabled function will not respond to any register reads
or writes.
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6300ESB ICH contains registers that are located in the processor’s I/O
6300ESB ICH incorporates multiple PCI functions as shown in
6300ESB ICH feature; a Hub Interface-to-PCI-X bridge.
Read Only: Writes to this register location generally have
no effect. However, in some cases, two separate registers
are located at the same location where a read will access
one register and a write will access the other register. See
the I/O and memory map tables for details.
Write Only: Reads to this register location generally
have no effect. However, in some cases, two separate
registers are located at the same location where a read
will access one register and a write will access the other
register. See the I/O and memory map tables for details.
Read/Write: A register with this attribute may be read
and written.
Read/Write Clear: A register bit with this attribute may
be read and written. However, writing a 1 will clear (sets
to zero) the corresponding bit, and writing a 0 will have
no effect.
When coming out of reset, the registers are set to
predetermined default states. It is the responsibility of
the system initialization software to determine
configuration, operating parameters, and optional system
features that are applicable, and to program the Intel
6300ESB ICH registers accordingly.
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6300ESB ICH I/O and memory
Intel
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6300ESB I/O Controller Hub
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6300ESB ICH;
6300ESB ICH
Table
142.
6
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DS