NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 415

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
Table 298. DEVTRAP_EN— Device Trap Enable Register
8.8.3.16 BUS_ADDR_TRACK— Bus Address Tracker
Table 299. BUS_ADDR_TRACK— Bus Address Tracker
8.8.3.17 BUS_CYC_TRACK— Bus Cycle Tracker
November 2007
Order Number: 300641-004US
15:0
Bits
Bits
Default Value:
I/O Address:
I/O Address:
2
1
0
Lockable:
Lockable:
®
Note: Usage: Legacy only.
Note: Usage: Legacy only.
Device:
Device:
6300ESB ICH
IDES0_TRP_EN
IDEP1_TRP_EN
IDEP0_TRP_EN
This register could be used by the SMI# handler to assist in determining what was the
last cycle from the processor. BUS_ADDR_TRACK may not contain “expected” last I/O
cycle data when Asynchronous SMIs and Synchronous SMIs are occurring
simultaneously. This register only reports “expected” last I/O cycle data when
Asynchronous SMIs are disabled.
This register could be used by the SMM handler to assist in determining what was the
last cycle from the processor. BUS_CYC_TRACK may not contain “expected” last I/O
cycle data when Asynchronous SMIs and Synchronous SMIs are occurring
simultaneously. This register only reports “expected” last I/O cycle data when
Asynchronous SMIs are disabled.
31
PMBASE +48h
0000h
No
Name
31
PMBASE +4Ch
No
Name
IDE Secondary Drive 0.
0 = Disable.
1 = Enable.
IDE Primary Drive 1.
0 = Disable.
1 = Enable.
IDE Primary Drive 0.
0 = Disable.
1 = Enable.
Corresponds to the low 16 bits of the last I/O cycle, as would
be defined by the PCI AD[15:0] signals on the PCI bus (even
though it may not be a real PCI cycle). The value is latched
based on SMI# active. This functionality is useful for figuring
out which I/O was last being accessed.
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Read/Write
16-bit
Core
0
Read-Only
16-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
Access
R/W
R/W
R/W
415
DS