NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 500

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

11.1.26 Offset 6C - 6Fh: USB EHCI Legacy Support
Table 404. Offset 6C - 6Fh: USB EHCI Legacy Support Extended Control/Status
Intel
DS
500
28:2
12:6
Bits
Default Value:
31
30
29
21
20
19
18
17
16
15
14
13
2
5
®
6300ESB I/O Controller Hub
Device:
Offset:
SMI on Async Advance
SMI on Async Advance
SMI on USB Complete
SMI on PCI Command
SMI on OS Ownership
SMI on PCI Command
SMI on OS Ownership
SMI on Host System
SMI on Port Change
SMI on BAR Enable
SMI on Frame List
SMI on USB Error
SMI on BAR
Extended Control/Status
(Sheet 1 of 2)
Reserved
Reserved
Rollover
Change
Detect
Enable
Enable
Enable
29
6C-6Fh
00000000h
Name
Error
This bit is set to ‘1’ whenever the Base Address Register
(BAR) is written.
This bit is set to ‘1’ whenever the PCI Command Register is
written.
This bit is set to ‘1’ whenever the HC OS Owned Semaphore
bit in the USB EHCI Legacy Support Extended Capability
register transitions from ’1’ to a ’0’ or ’0’ to a ‘1’.
Hardwired to 00h.
Shadow bit of the Interrupt on Async Advance bit in the
USB2STS register. To clear this bit system software must
write a ’1’ to the Interrupt on Async Advance bit in the
USB2STS register.
Shadow bit of Host System Error bit in the USB2STS. To clear
this bit, system software must write a ’1’ to the Host System
Error bit in the USB2STS register.
Shadow bit of Frame List Rollover bit in the USB2STS register.
To clear this bit system software must write a ’1’ to the Frame
List Rollover bit in the USB2STS register.
Shadow bit of Port Change Detect bit in the USB2STS register.
To clear this bit system software must write a ’1’ to the Port
Change Detect bit in the USB2STS register.
Shadow bit of USB Error Interrupt (USBERRINT) bit in the
USB2STS register. To clear this bit system software must
write a ’1’ to the USB Error Interrupt bit in the USB2STS
register.
Shadow bit of USB Interrupt (USBINT) bit in the USB2STS
register. To clear this bit system software must write a ’1’ to
the USB Interrupt bit in the USB2STS register.
When this bit is ‘1’ and SMI on BAR is ‘1’, the host controller
will issue an SMI.
When this bit is ‘1’ and SMI on PCI Command is ‘1’, the host
controller will issue an SMI.
When this bit is a ’1’ AND the OS Ownership Change bit is ’1’,
the host controller will issue an SMI.
Reserved—RO. Hardwired to 00h.
When this bit is a ’1’ and the SMI on Async Advance bit is a
’1’, the host controller will issue an SMI immediately.
Power Well:
Description
Attribute:
Function:
Size:
7
Read/Write
32-bit
Suspend
Order Number: 300641-004US
Intel
®
6300ESB ICH—11
November 2007
Access
R/WC
R/WC
R/WC
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO