NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 400

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8.8.3.6
Table 289. LV2—Level 2 Register
8.8.3.7
Intel
DS
400
Bits
Default Value:
7:0
I/O Address:
®
6300ESB I/O Controller Hub
Lockable:
Note: Usage: ACPI or Legacy.
Note: This register is symmetrical to the General Purpose Event 0 Enable Register. When the
Note: Usage: ACPI.
Device:
LV2—Level 2 Register
GPE0_STS—General Purpose Event 0 Status Register
corresponding _EN bit is set, and the _STS bit get set, the Intel
generate a Wake Event. Once back in an S0 state (or if already in an S0 state when the
event occurs), the Intel
is set, or an SMI# when the SCI_EN bit is not set. There will be no SCI/SMI# or wake
event on THRMOR_STS since there is no corresponding _EN bit. None of these bits are
reset by CF9h write. All are reset by RSMRST#.
31
PMBASE + 14h
(ACPI P_BLK + 4)
00h
No
Name
Reads to this register return all zeros, writes to this register
have no effect. Reads to this register generate a “enter a level
2 power state” (C2) to the clock control logic. This will cause
the STPCLK# signal to go active, and stay active until a break
event occurs. Throttling (due either to THTL_EN or THRM#
override) will be ignored.
®
6300ESB ICH will also generate an SCI when the SCI_EN bit
Power Well:
Description
Attribute:
Function:
Size:
0
Read-Only
8-bit
Core
Order Number: 300641-004US
®
6300ESB ICH will
Intel
®
6300ESB ICH—8
November 2007
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RO