NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 632

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 557. APIC1 Configuration Map (D29:F5) (Sheet 2 of 2)
17.1.1
Table 558. Offset 00 - 03h: VID_DID—Vendor/ID Register (APIC1—D29:F5)
17.1.2
Table 559. Offset 04 - 05h: APIC1CMD—APIC1 COMMAND Register (APIC1—
Intel
DS
632
15:0
15:0
15:9
Bits
Bits
Default Value:
Default Value:
8
7
®
6300ESB I/O Controller Hub
Lockable:
Lockable:
Device:
Device:
Offset:
Offset:
SERR_EN: SERR#
Vendor ID Value
Device ID Value
Offset 00 - 03h: VID_DID—Vendor/ID Register
(APIC1—D29:F5)
Offset 04 - 05h: APIC1CMD—APIC1 COMMAND
Register (APIC1—D29:F5)
D29:F5) (Sheet 1 of 2)
Reserved
Reserved
NOTES:
1. Refer to the Intel
Enable
29
00 - 03h
25ACh-8086h
No
Name
29
04-05h
0000h
No
Name
44-47h
50-51h
54-57h
Offset
value of the Revision ID Register.
Mnemonic
This is a 16-bit value assigned to the APIC1. DID = 25ACh
This is a 16-bit value assigned to Intel. Intel VID = 8086h
Reserved.
SERR# Enable controls the enable for the DO_SERR special
cycle on the hub interface.
0 = Disable special cycle.
1 = Enable special cycle.
Reserved.
MBAR
XSR
XID
®
6300ESB I/O Controller Hub Specification Update for the most up-to-date
Memory Base Register
PCI-X Identifiers
PCI-X Status
Register Name
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
5
Read-Only
32-bit
Core
5
Read/Write
16-bit
Core
Order Number: 300641-004US
000100EDh
FEC10000h
Default
Intel
0007h
®
6300ESB ICH—17
November 2007
Access
Access
R/W
Type
RO
RO
RO