NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 512

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

11.2.2.2 Offset CAPLENGTH + 04 - 07h: USB EHCI STS—USB EHCI
Table 413. Offset CAPLENGTH + 04 - 07h: USB EHCI STS—USB EHCI Status (Sheet
Intel
DS
512
31:1
11:6
Bits
Default Value:
15
14
13
12
6
5
®
6300ESB I/O Controller Hub
Note: This register indicates pending interrupts and various states of the Host Controller. The
Device:
Periodic Schedule Status
Offset:
Asynchronous Schedule
Interrupt on Async
Reclamation
Status
status resulting from a transaction on the serial bus is not indicated in this register.
Software sets a bit to ’0’ in this register by writing a ’1’ to it. See the Interrupts
description in Section 4 of the EHCI Specification for additional information concerning
USB EHCI interrupt conditions.
1 of 2)
Reserved
HCHalted
Reserved
Advance
Status
29
CAPLENGTH + 04-07h
00001000h
Name
Reserved. These bits are reserved and should be set to ’0’.
0 = Default. This bit reports the current real status of the
Asynchronous Schedule. When this bit is a ’0’, the status of
the Asynchronous Schedule is disabled. When this bit is a ’1’,
the status of the Asynchronous Schedule is enabled. The Host
Controller is not required to immediately disable or enable the
Asynchronous Schedule when software transitions the
Asynchronous Schedule Enable bit in the USBCMD register.
When this bit and the Asynchronous Schedule Enable bit are
the same value, the Asynchronous Schedule is either enabled
(1) or disabled (0).
0 = Default. This bit reports the current real status of the
Periodic Schedule. When this bit is a ’0’, the status of the
Periodic Schedule is disabled. When this bit is a ’1’, the status
of the Periodic Schedule is enabled. The Host Controller is not
required to immediately disable or enable the Periodic
Schedule when software transitions the Periodic Schedule
Enable bit in the USBCMD register. When this bit and the
Periodic Schedule Enable bit are the same value, the Periodic
Schedule is either enabled (1) or disabled (0).
0 = Default. This is a read-only status bit used to detect an
empty asynchronous schedule. The operational model and
valid transitions for this bit are described in Section 4 of the
EHCI Specification.
(Defaults to 1). This bit is a ’0’ whenever the Run/Stop bit is a
’1’. The Host Controller sets this bit to ’1’ after it has stopped
executing as a result of the Run/Stop bit being set to 0, either
by software or by the Host Controller hardware (e.g., internal
error).
Reserved.
0 = Default. System software may force the host controller to
issue an interrupt the next time the host controller advances
the asynchronous schedule by writing a ’1’ to the Interrupt on
Async Advance Doorbell bit in the USBCMD register. This bit
indicates the assertion of that interrupt source.
Description
Attribute:
Function:
Size:
7
Read/Write Clear
32-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—11
November 2007
Access
R/WC
RO
RO
RO
RO