NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 675

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18—Intel
18.6.1.27Offset 52: PX_SSTS—PCI-X Secondary Status
November 2007
Order Number: 300641-004US
15:0
08:0
Bits
05
04
03
9
6
Table 610. Offset 52: PX_SSTS—PCI-X Secondary Status (Sheet 1 of 2)
Note: This is the PCI-X command register which controls various modes of the bridge.
Unexpected
Completion
Completion
®
Secondary
Frequency
Device
Offset
Reserved
Delayed.
Overrun
Request
6300ESB ICH
Name
(SRD)
(SCO)
(USC)
(SCF)
Clock
Split
Split
Split
28
52
Reserved.
This field is set with the frequency of the secondary bus. The
values are:
Bits Max Frequency Clock Period
000
001
010
011
1xx
The default value for this register is given by
PCIXCAP=Bit 7 M66EN=Bit 6
This bit is set by a bridge when it cannot forward a
transaction on the secondary bus to the primary bus because
there is not enough room within the limit specified in the Split
Transaction Commitment Limit field in the Downstream Split
Transaction Control register.
NOTE: The Intel
This bit is set when a bridge terminates a Split Completion on
the secondary bus with retry or Disconnect at next ADB
because its buffers are full.
NOTE: The Intel
This bit is set when an unexpected split completion with a
requester ID equal to the Intel
bus number, device number 00h, and function number 0 is
received on the secondary interface. This bit is cleared by
software writing a ‘1’.
PCIXCAP M66ENPCI/X Freq
Mid
0
0
1
PCI Mode
66
[Not supported]
[Not supported]
Reserved
N/A
N/A
0
1
®
®
6300ESB ICH does not set this bit.
6300ESB ICH does not set this bit.
PCI-X 66 MHz
PCI-X 66 MHz
N/A
15
Reserved
Description
PCI
PCI
33 MHz
66 MHz
®
6300ESB ICH's secondary
Attribute:
Function
Size:
0
Read-Only
16-bit
Intel
®
Reset
Value
6300ESB I/O Controller Hub
00h
xxx
0
0
0
Access
R/WC
RO
RO
RO
RO
675
DS