NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 728

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

19.7.1.4 Latency
19.7.1.5 EOI/ISR Read Latency
19.7.1.6 Reset and Initialization
19.8
19.8.1
19.8.2
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6300ESB I/O Controller Hub
Latency for IRQ/Data updates over the SIU_SERIRQ bus in bridge-less systems with
the minimum Host supported IRQ/Data Frames of seventeen, will range up to 96 clocks
(2.88 µs with a 33MHz PCI Bus). If one or more PCI to PCI Bridge is added to a system,
the latency for IRQ/Data updates from the secondary or tertiary buses will be a few
clocks longer for synchronous buses, and approximately double for asynchronous
buses.
Any serialized IRQ scheme has a potential implementation issue related to IRQ latency.
IRQ latency could cause an EOI or ISR Read to precede an IRQ transition that it should
have followed. This could cause a system fault. The host interrupt controller is
responsible for ensuring that these latency issues are mitigated. The recommended
solution is to delay EOIs and ISR Reads to the interrupt controller by the same amount
as the SIU_SERIRQ Cycle latency in order to ensure that these events do not occur out
of order.
The SIU_SERIRQ bus uses SIU_LRESET# as its reset signal. The SIU_SERIRQ pin is tri-
stated by all agents while SIU_LRESET# is active. With reset, SIU_SERIRQ Slaves are
put into the (continuous) IDLE mode. The Host Controller is responsible for starting the
initial SIU_SERIRQ Cycle to collect system’s IRQ/Data default values. The system then
follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for
subsequent SIU_SERIRQ Cycles. It is Host Controller’s responsibility to provide the
default values to the Interrupt controller and other system logic before the first
SIU_SERIRQ Cycle is performed. For SIU_SERIRQ system suspend, insertion, or
removal application, the Host controller should be programmed into Continuous (IDLE)
mode first. This is to ensure that the SIU_SERIRQ bus is in IDLE state before the
system configuration changes.
Configuration
The Configuration of the SIU is very flexible and is based on the configuration
architecture implemented in typical Plug-and-Play components. The SIU is designed for
motherboard applications in which the resources required by their components are
known. With its flexible resource allocation architecture, the SIU allows the BIOS to
assign resources at POST.
Configuration Port Address Selection
The SIU configuration port addresses for INDEX and DATA are fixed at 4Eh/4Fh.
See also
D31:F0)” on page
Primary Configuration Address Decoder
After a PCI Reset (SIU_LRESET# pin asserted) or Power On Reset the SIU is in the Run
Mode with the two UARTs disabled. They may be configured through two standard
Configuration I/O Ports (INDEX and DATA) by placing the SIU into Configuration Mode.
Section 8.1.31, “Offset E6h - E7h: LPC_EN—LPC I/F Enables (LPC I/F—
337.
Order Number: 300641-004US
Intel
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6300ESB ICH—19
November 2007