NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 252
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NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
Lead Free Status / RoHS Status
Compliant
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5.19.8.1 Format of Slave Write Cycle
Table 131. Slave Write Cycle Format
Intel
DS
252
®
6300ESB I/O Controller Hub
Note: The external microcontroller should not attempt to access the Intel
Note: When an external microcontroller accesses the SMBus Slave Interface over the SMLink
SMBus slave logic until 1 second after both: RTEST# is high and RSMRST# is high.
When a master leaves the clock and data bits of the SMLink interface at ‘1’ for 50 µs or
more in the middle of a cycle, the Intel
undefined. This is interpreted as an unexpected idle and should be avoided when
performing management activities to the slave logic.
a translation in the address is needed to accommodate the least significant bit used for
read/write control. For example, when the Intel
(RCV_SLVA) is left at 44h (default), the external microcontroller would use an address
of 88h/89h (write/read).
The external master performs Byte Write commands to the Intel
Slave I/F. The “Command” field (bits 11
The Data field (bits 20
The Write Cycle format is shown in
the registers.
11–18
20–27
Bits
2–8
10
19
28
29
1
9
— Bit 16 of the SMI Status Register
all others.
Start Condition
Slave Address - 7
bits
Write
ACK
Command
ACK
Register Data
ACK
Stop
Description
-
27) indicates the value that should be written to that register.
External
Microcontroller
External
Microcontroller
External
Microcontroller
Intel
ICH
External
Microcontroller
Intel
ICH
External
Microcontroller
Intel
ICH
External
Microcontroller
®
®
®
Driven by
6300ESB
6300ESB
6300ESB
Table
(Section 8.8.3.10, “SMI_STS—SMI Status
®
-
18) indicate which register is being accessed.
131.
6300ESB ICH slave logic’s behavior is
Table 132
®
Must match value in Receive Slave
Address register.
Always 0
This field indicates which register will be
accessed.
See
definitions
See
definitions
6300ESB ICH slave address
Table 132
Table 132
has the values associated with
below for the register
below for the register
Comment
Order Number: 300641-004US
®
6300ESB ICH SMBus
Intel
®
6300ESB ICH’s
®
6300ESB ICH—5
Register”) for
November 2007
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